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Message-Id: <1484918557-15481-4-git-send-email-grzegorz.andrejczuk@intel.com>
Date: Fri, 20 Jan 2017 14:22:35 +0100
From: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
To: tglx@...utronix.de, mingo@...hat.com, hpa@...or.com, x86@...nel.org
Cc: linux-kernel@...r.kernel.org, Piotr.Luc@...el.com,
dave.hansen@...ux.intel.com,
Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
Subject: [PATCH v12 3/5] x86/cpufeature: add RING3MWAIT to CPU features
Add software-defined CPUID bit for the non-architectural ring 3
MONITOR/MWAIT feature.
Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
---
arch/x86/include/asm/cpufeatures.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index eafee31..167e140 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -100,7 +100,7 @@
#define X86_FEATURE_XTOPOLOGY ( 3*32+22) /* cpu topology enum extensions */
#define X86_FEATURE_TSC_RELIABLE ( 3*32+23) /* TSC is known to be reliable */
#define X86_FEATURE_NONSTOP_TSC ( 3*32+24) /* TSC does not stop in C states */
-/* free, was #define X86_FEATURE_CLFLUSH_MONITOR ( 3*32+25) * "" clflush reqd with monitor */
+#define X86_FEATURE_RING3MWAIT ( 3*32+25) /* ring 3 MONITOR/MWAIT */
#define X86_FEATURE_EXTD_APICID ( 3*32+26) /* has extended APICID (8 bits) */
#define X86_FEATURE_AMD_DCM ( 3*32+27) /* multi-node processor */
#define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
--
2.5.1
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