linux-kernel - Re: [RESEND PATCHv1 5/8] mmc: sdhci-msm: configure CORE_CSR_CDC_DELAY

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Message-ID: <e7b37b16-3d87-3766-6e03-9f67cd29b64a@codeaurora.org>
Date:   Fri, 20 Jan 2017 09:42:11 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Ritesh Harjani <riteshh@...eaurora.org>, adrian.hunter@...el.com,
        ulf.hansson@...aro.org
Cc:     linux-mmc@...r.kernel.org, linux-kernel@...r.kernel.org,
        shawn.lin@...k-chips.com, linux-arm-msm@...r.kernel.org,
        georgi.djakov@...aro.org, asutoshd@...eaurora.org,
        stummala@...eaurora.org, venkatg@...eaurora.org,
        pramod.gurav@...aro.org, jeremymc@...hat.com, git@...r.de,
        Subhash Jadavani <subhashj@...eaurora.org>
Subject: Re: [RESEND PATCHv1 5/8] mmc: sdhci-msm: configure
 CORE_CSR_CDC_DELAY_CFG to recommended value

On 01/09/2017 11:00 PM, Ritesh Harjani wrote:
> From: Subhash Jadavani <subhashj@...eaurora.org>
>
> Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay.
> We may see data CRC errors if it's programmed for any other delay
> value.
>
> Signed-off-by: Subhash Jadavani <subhashj@...eaurora.org>
> Signed-off-by: Ritesh Harjani <riteshh@...eaurora.org>
> ---
>  drivers/mmc/host/sdhci-msm.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index a028568..84d29dd 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -679,7 +679,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host)
>  	writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1);
>  	writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG);
>  	writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG);
> -	writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
> +	writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG);
>  	writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG);
>  	writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);
>  

There's a comment block above this set of writes that repeats what's
happening in the code.

        /*
         * Perform CDC Register Initialization Sequence
         *
         * CORE_CSR_CDC_CTLR_CFG0       0x11800EC
         * CORE_CSR_CDC_CTLR_CFG1       0x3011111
         * CORE_CSR_CDC_CAL_TIMER_CFG0  0x1201000
         * CORE_CSR_CDC_CAL_TIMER_CFG1  0x4
         * CORE_CSR_CDC_REFCOUNT_CFG    0xCB732020
         * CORE_CSR_CDC_COARSE_CAL_CFG  0xB19
         * CORE_CSR_CDC_DELAY_CFG       0x3AC
         * CORE_CDC_OFFSET_CFG          0x0
         * CORE_CDC_SLAVE_DDA_CFG       0x16334
         */

Perhaps we should just delete those comments because they're incorrect now.

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