linux-kernel - Re: [PATCH v2 1/3] clk: bcm2835: Don't rate change PLLs on behalf of DSI PLL dividers.

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Date:   Fri, 20 Jan 2017 16:23:44 -0800
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Eric Anholt <eric@...olt.net>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Michael Turquette <mturquette@...libre.com>,
        linux-rpi-kernel@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Stephen Warren <swarren@...dotorg.org>,
        Lee Jones <lee@...nel.org>,
        bcm-kernel-feedback-list@...adcom.com, linux-clk@...r.kernel.org
Subject: Re: [PATCH v2 1/3] clk: bcm2835: Don't rate change PLLs on behalf of
 DSI PLL dividers.

On 01/18, Eric Anholt wrote:
> Our core PLLs are intended to be configured once and left alone.  With
> the SET_RATE_PARENT, asking to set the PLLD_DSI1 clock rate would
> change PLLD just to get closer to the requested DSI clock, thus
> changing PLLD_PER, the UART and ethernet PHY clock rates downstream of
> it, and breaking ethernet.
> 
> We *do* want PLLH to change so that PLLH_AUX can be exactly the value
> we want, though.  Thus, we need to have a per-divider policy of
> whether to pass rate changes up.
> 
> Signed-off-by: Eric Anholt <eric@...olt.net>
> ---

Applied to clk-next

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