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Date:   Mon, 23 Jan 2017 11:05:49 +0100
From:   Andrzej Hajda <a.hajda@...sung.com>
To:     Inki Dae <inki.dae@...sung.com>, dri-devel@...ts.freedesktop.org,
        Krzysztof Kozlowski <krzk@...nel.org>
Cc:     Andrzej Hajda <a.hajda@...sung.com>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
        Marek Szyprowski <m.szyprowski@...sung.com>,
        Kyungmin Park <kyungmin.park@...sung.com>,
        linux-kernel@...r.kernel.org, linux-samsung-soc@...r.kernel.org
Subject: [PATCH v3 7/7] arm64: dts: exynos: configure TV path clocks for Ultra
 HD modes

Ultra HD modes requires clock ticking at increased rate.

Signed-off-by: Andrzej Hajda <a.hajda@...sung.com>
---
v2: long lines wrapped
v3: moved assigned clocks to cmu_disp node in tm2-common
---
 arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
index cd8847b..5f1e172 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
@@ -217,6 +217,18 @@
 	assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
 };
 
+&cmu_disp {
+	assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DECON_TV_ECLK_A>,
+			  <&cmu_mif CLK_DIV_SCLK_DECON_TV_ECLK>,
+			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>,
+			  <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK>;
+	assigned-clock-parents = <&cmu_mif CLK_MOUT_BUS_PLL_DIV2>,
+				 <0>,
+				 <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
+				 <&cmu_disp CLK_MOUT_SCLK_DECON_TV_ECLK_USER>;
+	assigned-clock-rates = <0>, <400000000>;
+};
+
 &cmu_fsys {
 	assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
 		<&cmu_top CLK_MOUT_SCLK_USBHOST30>,
-- 
2.7.4

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