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Message-ID: <CAPDyKFpX14Ojse_0gZZtQiUtSP_w9tN+Wu5OBx2Uv42FLSY5OA@mail.gmail.com>
Date: Tue, 24 Jan 2017 09:18:46 +0100
From: Ulf Hansson <ulf.hansson@...aro.org>
To: Maxime Ripard <maxime.ripard@...e-electrons.com>
Cc: Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh+dt@...nel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
Andre Przywara <andre.przywara@....com>
Subject: Re: [PATCH v3 5/13] mmc: sunxi: Mask DATA0 when updating the clock
On 16 January 2017 at 17:56, Maxime Ripard
<maxime.ripard@...e-electrons.com> wrote:
> The A64 MMC controllers need DATA0 to be masked while updating the clock,
> otherwise any subsequent command will result in a timeout.
Could you elaborate on what mask DATA0 really means? I don't follow.
Kind regards
Uffe
>
> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com>
> ---
> drivers/mmc/host/sunxi-mmc.c | 14 +++++++++++++-
> 1 file changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 51d6388a194e..6bbe61397b7c 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -101,6 +101,7 @@
> (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET)
>
> /* clock control bits */
> +#define SDXC_MASK_DATA0 BIT(31)
> #define SDXC_CARD_CLOCK_ON BIT(16)
> #define SDXC_LOW_POWER_ON BIT(17)
>
> @@ -254,6 +255,9 @@ struct sunxi_mmc_cfg {
> /* does the IP block support autocalibration? */
> bool can_calibrate;
>
> + /* Does DATA0 needs to be masked while the clock is updated */
> + bool mask_data0;
> +
> bool needs_new_timings;
> };
>
> @@ -657,10 +661,12 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
> u32 rval;
>
> rval = mmc_readl(host, REG_CLKCR);
> - rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
> + rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0);
>
> if (oclk_en)
> rval |= SDXC_CARD_CLOCK_ON;
> + if (host->cfg->mask_data0)
> + rval |= SDXC_MASK_DATA0;
>
> mmc_writel(host, REG_CLKCR, rval);
>
> @@ -680,6 +686,11 @@ static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
> return -EIO;
> }
>
> + if (host->cfg->mask_data0) {
> + rval = mmc_readl(host, REG_CLKCR);
> + mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0);
> + }
> +
> return 0;
> }
>
> @@ -1081,6 +1092,7 @@ static const struct sunxi_mmc_cfg sun50i_a64_cfg = {
> .idma_des_size_bits = 16,
> .clk_delays = NULL,
> .can_calibrate = true,
> + .mask_data0 = true,
> .needs_new_timings = true,
> };
>
> --
> git-series 0.8.11
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