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Date:   Tue, 24 Jan 2017 09:27:44 -0500
From:   Christopher Covington <>
To:     Mark Rutland <>,
        Catalin Marinas <>
Cc:     Mark Langsdorf <>,,
        Jonathan Corbet <>,
        Marc Zyngier <>,
        Jon Masters <>,,, Will Deacon <>,, Paolo Bonzini <>,,
Subject: Re: [PATCH v3 2/5] arm64: Work around Falkor erratum 1003

On 01/12/2017 11:12 AM, Mark Rutland wrote:
> On Thu, Jan 12, 2017 at 03:45:48PM +0000, Catalin Marinas wrote:
>> On Wed, Jan 11, 2017 at 06:40:52PM +0000, Mark Rutland wrote:
>>> Likewise, I beleive we may need to modify cpu_set_reserved_ttbr0().
>> This may be fine if my assumptions about this erratum are correct. In
>> the cpu_set_reserved_ttbr0() case we set TTBR0_EL1 to a table without
>> any entries, so no new entries could be tagged with the old ASID.
> For some reason, I was under the impression that the issue was old table
> entries being allocated to the new ASID. Looking over the series again,
> it's not clear to me precisely which cases can occur.
> It would be good to see that clarified.

I'll add more general background the commit message in the next revision
and I've also asked directly about this. The answer is that page table
entries using the new translation table base address will be allocated
into the TLB using the old ASID. If employing the workaround, it's
possible for page table entries using the new translation table base
to be allocated into the TLB using the reserved ASID.


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