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Message-ID: <98393c2c-4d1e-d8bb-b693-ec26ea919a4c@zytor.com>
Date: Wed, 25 Jan 2017 12:34:07 -0800
From: "H. Peter Anvin" <hpa@...or.com>
To: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>,
Ingo Molnar <mingo@...hat.com>,
Thomas Gleixner <tglx@...utronix.de>,
Andy Lutomirski <luto@...nel.org>, Borislav Petkov <bp@...e.de>
Cc: Peter Zijlstra <peterz@...radead.org>,
Andrew Morton <akpm@...ux-foundation.org>,
Brian Gerst <brgerst@...il.com>,
Chris Metcalf <cmetcalf@...lanox.com>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Paolo Bonzini <pbonzini@...hat.com>,
Liang Z Li <liang.z.li@...el.com>,
Masami Hiramatsu <mhiramat@...nel.org>,
Huang Rui <ray.huang@....com>, Jiri Slaby <jslaby@...e.cz>,
Jonathan Corbet <corbet@....net>,
"Michael S. Tsirkin" <mst@...hat.com>,
Paul Gortmaker <paul.gortmaker@...driver.com>,
Vlastimil Babka <vbabka@...e.cz>,
Chen Yucong <slaoub@...il.com>,
Alexandre Julliard <julliard@...ehq.org>,
Fenghua Yu <fenghua.yu@...el.com>, Stas Sergeev <stsp@...t.ru>,
"Ravi V. Shankar" <ravi.v.shankar@...el.com>,
Shuah Khan <shuah@...nel.org>, linux-kernel@...r.kernel.org,
x86@...nel.org, linux-msdos@...r.kernel.org, wine-devel@...ehq.org
Subject: Re: [v3 PATCH 00/10] x86: Enable User-Mode Instruction Prevention
On 01/25/17 12:23, Ricardo Neri wrote:
> * SMSW returns the value with which the CR0 register is programmed in
> head_32/64.S at boot time. This is, the following bits are enabed:
> CR0.0 for Protection Enable, CR.1 for Monitor Coprocessor, CR.4 for
> Extension Type, which will always be 1 in recent processors with UMIP;
> CR.5 for Numeric Error, CR0.16 for Write Protect, CR0.18 for Alignment
> Mask. Additionally, in x86_64, CR0.31 for Paging is set.
SMSW only returns CR0[15:0], so the reference here to CR0[31:16] seems odd.
-hpa
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