linux-kernel - RE: [PATCH net-next v2] macb: Common code to enable ptp support for MACB/GEM

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Message-ID: <BN3PR07MB25163747E1520E4CE1C6164FC9760@BN3PR07MB2516.namprd07.prod.outlook.com>
Date:   Fri, 27 Jan 2017 10:26:14 +0000
From:   Rafal Ozieblo <rafalo@...ence.com>
To:     Harini Katakam <harinikatakamlinux@...il.com>
CC:     Andrei Pistirica <andrei.pistirica@...rochip.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "nicolas.ferre@...el.com" <nicolas.ferre@...el.com>,
        "harini.katakam@...inx.com" <harini.katakam@...inx.com>,
        "punnaia@...inx.com" <punnaia@...inx.com>,
        "michals@...inx.com" <michals@...inx.com>,
        "anirudh@...inx.com" <anirudh@...inx.com>,
        "boris.brezillon@...e-electrons.com" 
        <boris.brezillon@...e-electrons.com>,
        "alexandre.belloni@...e-electrons.com" 
        <alexandre.belloni@...e-electrons.com>,
        "tbultel@...elsurmer.com" <tbultel@...elsurmer.com>,
        "richardcochran@...il.com" <richardcochran@...il.com>
Subject: RE: [PATCH net-next v2] macb: Common code to enable ptp support for
 MACB/GEM

>-----Original Message-----
>From: Harini Katakam [mailto:harinikatakamlinux@...il.com] 
>Sent: 27 stycznia 2017 06:43
>Subject: Re: [PATCH net-next v2] macb: Common code to enable ptp support for MACB/GEM
>
>Hi Rafal,
>
>On Thu, Jan 26, 2017 at 8:45 PM, Rafal Ozieblo <rafalo@...ence.com> wrote:
>>> -----Original Message-----
>>> From: Andrei Pistirica [mailto:andrei.pistirica@...rochip.com]
>>> Sent: 19 stycznia 2017 16:56
>>> Subject: [PATCH net-next v2] macb: Common code to enable ptp support for MACB/GEM
>>>
>>>
>>> +static inline bool gem_has_ptp(struct macb *bp)
>>> +{
>>> +     return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
>>> +}
>> Why don't you use hardware capabilities here? Would it be better to read it from hardware instead adding it to many configuration?
>
>If you are referring to TSU bit in DCFG5, then we will be relying on
>Cadence IP's information irrespective of the SoC capability
>and whether the PTP support was adequate.
>I think the capability approach gives better control and
>it is not really much to add.
>
>Regards,
>Harini
>
Yes, I'm referring to TSU bit.
What if SoC contains multiple Cadence GEMs, some with PTP support and others without?
Relevant will be checking both, hardware capabilities and SoC capabilities from "caps" field.