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Date:   Sat, 28 Jan 2017 22:56:56 +0100
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Rob Herring <robh@...nel.org>
Cc:     "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Hans Ulli Kroll <ulli.kroll@...glemail.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Janos Laube <janos.dev@...il.com>,
        Paulius Zaleckas <paulius.zaleckas@...il.com>,
        openwrt-devel@...nwrt.org, Arnd Bergmann <arnd@...db.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>
Subject: Re: [PATCH 11/22] ARM: dts: add top-level DT bindings for Cortina Gemini

On Mon, Jan 23, 2017 at 9:21 PM, Rob Herring <robh@...nel.org> wrote:
> On Sun, Jan 22, 2017 at 01:22:19PM +0100, Linus Walleij wrote:
>> This adds the top level SoC bindings for Cortina systems Gemini
>> platforms.
(...)
>> +- intcon: the root node must have an interrupt controller node pointing to
>
> intcon is just a source label and not meaningful for the binding.

OK

>> +Example:
>> +
>> +/ {
>> +     interrupt-parent = <&intcon>;
>> +
>> +     syscon: syscon@...00000 {
>
> This chip has no internal bus? Put all these nodes under a bus.

Are you thinking something of the form:

        soc: soc {
                #address-cells = <1>;
                #size-cells = <1>;
                ranges;
                compatible = "simple-bus";

                syscon: syscon@...00000 {

(...)

?

Yours,
Linus Walleij

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