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Date:   Sun, 29 Jan 2017 18:15:41 -0500 (EST)
From:   David Miller <davem@...emloft.net>
To:     Alexey.Brodkin@...opsys.com
Cc:     netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
        peppe.cavallaro@...com, fabrice.gasnier@...com, manabian@...il.com,
        preid@...ctromag.com.au, alexandre.torgue@...il.com,
        Vineet.Gupta1@...opsys.com
Subject: Re: [PATCH] stmmac: Discard masked flags in interrupt status
 register

From: Alexey Brodkin <Alexey.Brodkin@...opsys.com>
Date: Fri, 27 Jan 2017 15:24:43 +0300

> DW GMAC databook says the following about bits in "Register 15 (Interrupt
> Mask Register)":
> --------------------------->8-------------------------
> When set, this bit __disables_the_assertion_of_the_interrupt_signal__
> because of the setting of XXX bit in Register 14 (Interrupt
> Status Register).
> --------------------------->8-------------------------
> 
> In fact even if we mask one bit in the mask register it doesn't prevent
> corresponding bit to appear in the status register, it only disables
> interrupt generation for corresponding event.
> 
> But currently we expect a bit different behavior: status bits to be in
> sync with their masks, i.e. if mask for bit A is set in the mask
> register then bit A won't appear in the interrupt status register.
> 
> This was proven to be incorrect assumption, see discussion here [1].
> That misunderstanding causes unexpected behaviour of the GMAC, for
> example we were happy enough to just see bogus messages about link
> state changes.
> 
> So from now on we'll be only checking bits that really may trigger an
> interrupt.
> 
> [1] https://lkml.org/lkml/2016/11/3/413
> 
> Signed-off-by: Alexey Brodkin <abrodkin@...opsys.com>

This looks good, applied, thanks.

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