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Message-ID: <20170130074404.d7mi6h4kviornr5s@lukather>
Date: Mon, 30 Jan 2017 08:44:04 +0100
From: maxime.ripard@...e-electrons.com
To: Icenowy Zheng <icenowy@...c.xyz>
Cc: Srinivas Kandagatla <srinivas.kandagatla@...aro.org>,
Chen-Yu Tsai <wens@...e.org>, Rob Herring <robh+dt@...nel.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com
Subject: Re: [PATCH v2 1/2] nvmem: sunxi-sid: add support for H3 and A64's
SID controller
On Sun, Jan 29, 2017 at 09:56:40AM +0800, Icenowy Zheng wrote:
> H3 and A64 SoCs have a bigger SID controller, which has its direct read
> address at 0x200 position in the SID block, not 0x0.
>
> Also, H3 SID controller has some silicon bug that makes the direct read
> value wrong at first, add code to workaround the bug. (This bug has
> already been fixed on A64 and later SoCs)
>
> Signed-off-by: Icenowy Zheng <icenowy@...c.xyz>
Please split that into several patches. One to allow to set the size
through the structure, one to support the A64, and one to support the
H3.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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