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Message-Id: <3vClL26Q2hz9rxw@ozlabs.org>
Date: Wed, 1 Feb 2017 12:05:30 +1100 (AEDT)
From: Michael Ellerman <patch-notifications@...erman.id.au>
To: "Gautham R. Shenoy" <ego@...ux.vnet.ibm.com>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Paul Mackerras <paulus@...ba.org>,
"Rafael J. Wysocki" <rjw@...ysocki.net>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Michael Neuling <mikey@...ling.org>,
Vaidyanathan Srinivasan <svaidy@...ux.vnet.ibm.com>,
"Shreyas B. Prabhu" <shreyasbp@...il.com>,
Shilpasri G Bhat <shilpa.bhat@...ux.vnet.ibm.com>,
Stewart Smith <stewart@...ux.vnet.ibm.com>,
Balbir Singh <bsingharora@...il.com>,
"Oliver O'Halloran" <oohall@...il.com>,
Rob Herring <robh+dt@...nel.org>
Cc: mark.rutland@....com, devicetree@...r.kernel.org,
"Gautham R. Shenoy" <ego@...ux.vnet.ibm.com>,
linux-pm@...r.kernel.org, linux-kernel@...r.kernel.org,
linuxppc-dev@...ts.ozlabs.org
Subject: Re: [v6,1/5] powernv:idle: Add IDLE_STATE_ENTER_SEQ_NORET macro
On Wed, 2017-01-25 at 08:36:25 UTC, "Gautham R. Shenoy" wrote:
> From: "Gautham R. Shenoy" <ego@...ux.vnet.ibm.com>
>
> Currently all the low-power idle states are expected to wake up
> at reset vector 0x100. Which is why the macro IDLE_STATE_ENTER_SEQ
> that puts the CPU to an idle state and never returns.
>
> On ISA v3.0, when the ESL and EC bits in the PSSCR are zero, the CPU
> is expected to wake up at the next instruction of the idle
> instruction.
>
> This patch adds a new macro named IDLE_STATE_ENTER_SEQ_NORET for the
> no-return variant and reuses the name IDLE_STATE_ENTER_SEQ
> for a variant that allows resuming operation at the instruction next
> to the idle-instruction.
>
> Acked-by: Balbir Singh <bsingharora@...il.com>
> Signed-off-by: Gautham R. Shenoy <ego@...ux.vnet.ibm.com>
Series applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/823b7bd5156a93872d9561b3f033df
cheers
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