linux-kernel - Re: [Intel-gfx] [PATCH v2] drm/i915: Flush untouched framebuffers before display on !llc

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20170201104854.GB12889@nuc-i3427.alporthouse.com>
Date:   Wed, 1 Feb 2017 10:48:54 +0000
From:   Chris Wilson <chris@...is-wilson.co.uk>
To:     linux-kernel@...r.kernel.org, intel-gfx@...ts.freedesktop.org,
        lkml@...garu.com,
        "# v4 . 10-rc1+" <drm-intel-fixes@...ts.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Flush untouched framebuffers
 before display on !llc

On Wed, Feb 01, 2017 at 11:24:32AM +0100, Daniel Vetter wrote:
> On Mon, Jan 09, 2017 at 11:19:32AM +0000, Chris Wilson wrote:
> > On a non-llc system, the objects are created with .cache_level =
> > CACHE_NONE and so the transition to uncached for scanout is a no-op.
> > However, if the object was never written to, it will still be in the CPU
> > domain (having been zeroed out by shmemfs). Those cachelines need to be
> > flushed prior to display.
> > 
> > Reported-by: Vito Caputo
> > Fixes: a6a7cc4b7db6 ("drm/i915: Always flush the dirty CPU cache when pinning the scanout")
> > Signed-off-by: Chris Wilson <chris@...is-wilson.co.uk>
> > Cc: <drm-intel-fixes@...ts.freedesktop.org> # v4.10-rc1+
> > ---
> >  drivers/gpu/drm/i915/i915_gem.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 76689b59fc90..bdb113ef8cfe 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -3514,7 +3514,7 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
> >  	vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
> >  
> >  	/* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
> > -	if (obj->cache_dirty) {
> > +	if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
> 
> Alternatively, should we set cache_dirty when initially allocating an
> object? Ofc only if cpu_cache_is_coherent, like we do in other places.

I thought about it and didn't come to any firm conclusion. Currently
"cache_dirty" means omission of clflush, and that's been a source of
confusion ever since. I've a patch/plan to do async clflushing which
similarly impacts upon the meaning of obj->cache_dirty and interation
with frontbuffer tracking, so that seems a reasonable point to which to
defer further thought.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre