lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Thu, 2 Feb 2017 13:20:31 -0600
From:   Dinh Nguyen <dinh.linux@...il.com>
To:     thor.thayer@...ux.intel.com
Cc:     Dinh Nguyen <dinguyen@...nsource.altera.com>,
        dinh.nguyen@...ux.intel.com, Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Russell King <linux@...linux.org.uk>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        Linux List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: dts: Add EMAC AXI settings for Arria10

On Thu, Feb 2, 2017 at 11:09 AM,  <thor.thayer@...ux.intel.com> wrote:
> From: Thor Thayer <thor.thayer@...ux.intel.com>
>
> Add the device tree entries needed to support the EMAC AXI
> bus settings on the Arria10 SoCFPGA chip.
>
> Signed-off-by: Thor Thayer <thor.thayer@...ux.intel.com>
> ---
>  arch/arm/boot/dts/socfpga_arria10.dtsi | 7 +++++++
>  1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
> index f520cbf..f05dd15 100644
> --- a/arch/arm/boot/dts/socfpga_arria10.dtsi
> +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
> @@ -400,6 +400,12 @@
>                                 };
>                 };
>
> +               socfpga_axi_setup: stmmac-axi-config {
> +                       snps,wr_osr_lmt = <0xf>;
> +                       snps,rd_osr_lmt = <0xf>;
> +                       snps,blen = <0 0 0 0 16 0 0>;
> +               };
> +
>                 gmac0: ethernet@...00000 {
>                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
>                         altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> @@ -416,6 +422,7 @@
>                         clock-names = "stmmaceth";
>                         resets = <&rst EMAC0_RESET>;
>                         reset-names = "stmmaceth";
> +                       snps,axi-config = <&socfpga_axi_setup>;

What about gmac1 and gmac2? They probably need this entry as well.

Dinh

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ