linux-kernel - [tip:x86/cpufeature] x86/cpufeature: Enable RING3MWAIT for Knights Landing

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Message-ID: <tip-e16fd002afe2b16d828bbf738b8a81a185fe9272@git.kernel.org>
Date:   Sat, 4 Feb 2017 08:32:24 -0800
From:   tip-bot for Grzegorz Andrejczuk <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     grzegorz.andrejczuk@...el.com, linux-kernel@...r.kernel.org,
        hpa@...or.com, mingo@...nel.org, tglx@...utronix.de
Subject: [tip:x86/cpufeature] x86/cpufeature: Enable RING3MWAIT for Knights
 Landing

Commit-ID:  e16fd002afe2b16d828bbf738b8a81a185fe9272
Gitweb:     http://git.kernel.org/tip/e16fd002afe2b16d828bbf738b8a81a185fe9272
Author:     Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
AuthorDate: Fri, 20 Jan 2017 14:22:36 +0100
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Sat, 4 Feb 2017 08:51:09 +0100

x86/cpufeature: Enable RING3MWAIT for Knights Landing

Enable ring 3 MONITOR/MWAIT for Intel Xeon Phi x200 codenamed Knights
Landing.

Presence of this feature cannot be detected automatically (by reading any
other MSR) therefore it is required to explicitly check for the family and
model of the CPU before attempting to enable it.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
Cc: Piotr.Luc@...el.com
Cc: dave.hansen@...ux.intel.com
Link: http://lkml.kernel.org/r/1484918557-15481-5-git-send-email-grzegorz.andrejczuk@intel.com
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>

---
 Documentation/admin-guide/kernel-parameters.txt |  4 +++
 arch/x86/kernel/cpu/intel.c                     | 37 +++++++++++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index be7c0d9..cfbb3fc 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3563,6 +3563,10 @@
 	rhash_entries=	[KNL,NET]
 			Set number of hash buckets for route cache
 
+	ring3mwait=disable
+			[KNL] Disable ring 3 MONITOR/MWAIT feature on supported
+			CPUs.
+
 	ro		[KNL] Mount root device read-only on boot
 
 	rodata=		[KNL]
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 203f860..da2401a 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -15,6 +15,8 @@
 #include <asm/cpu.h>
 #include <asm/intel-family.h>
 #include <asm/microcode_intel.h>
+#include <asm/hwcap2.h>
+#include <asm/elf.h>
 
 #ifdef CONFIG_X86_64
 #include <linux/topology.h>
@@ -62,6 +64,39 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
 	}
 }
 
+static bool ring3mwait_disabled __read_mostly;
+
+static int __init ring3mwait_disable(char *__unused)
+{
+	ring3mwait_disabled = true;
+	return 0;
+}
+__setup("ring3mwait=disable", ring3mwait_disable);
+
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+	/*
+	 * Ring 3 MONITOR/MWAIT feature cannot be detected without
+	 * cpu model and family comparison.
+	 */
+	if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
+		return;
+
+	if (ring3mwait_disabled) {
+		msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
+			      MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+		return;
+	}
+
+	msr_set_bit(MSR_MISC_FEATURE_ENABLES,
+		    MSR_MISC_FEATURE_ENABLES_RING3MWAIT_BIT);
+
+	set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
+
+	if (c == &boot_cpu_data)
+		ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
+}
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
 	u64 misc_enable;
@@ -560,6 +595,8 @@ static void init_intel(struct cpuinfo_x86 *c)
 		detect_vmx_virtcap(c);
 
 	init_intel_energy_perf(c);
+
+	probe_xeon_phi_r3mwait(c);
 }
 
 #ifdef CONFIG_X86_32