linux-kernel - Re: [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver

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Message-ID: <3508420.z4eX5F6ytJ@phil>
Date:   Sun, 05 Feb 2017 10:41:23 +0100
From:   Heiko Stuebner <heiko@...ech.de>
To:     Frank Wang <frank.wang@...k-chips.com>
Cc:     johnyoun@...opsys.com, gregkh@...uxfoundation.org,
        linux-kernel@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-rockchip@...ts.infradead.org, huangtao@...k-chips.com,
        kever.yang@...k-chips.com, william.wu@...k-chips.com
Subject: Re: [RESEND PATCH 0/1] add multiple clock handling for dwc2 driver

Hi Frank,

Am Sonntag, 5. Februar 2017, 10:51:00 CET schrieb Frank Wang:
> The original posting on Jan 19th have not received any responses, so I
> resend them.
> 
> The Current default dwc2 just handle one clock named otg, however, it may
> have two or more clock need to manage for some new SoCs(such as RK3328), so
> this adds change clk to clk's array of dwc2_hsotg to handle more clocks
> operation.

can you please give a bit more detail on the specific layout.

I guess you're talking about hclk_otg_pmu, right? What component does it 
supply, because I didn't find anything in the partial TRM in the PMU section 
relating to the "otg".

This meant to make sure, you're actually controlling some part of the dwc2 
with that second/third/... clock and not some separate component.


Heiko