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Message-ID: <9974653ab84040c3b12fad075790c123@svr-chch-ex1.atlnz.lc>
Date: Mon, 6 Feb 2017 23:25:23 +0000
From: Chris Packham <Chris.Packham@...iedtelesis.co.nz>
To: Stephen Boyd <sboyd@...eaurora.org>
CC: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
Michael Turquette <mturquette@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Jason Cooper <jason@...edaemon.net>,
Andrew Lunn <andrew@...n.ch>,
"Gregory Clement" <gregory.clement@...e-electrons.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Russell King <linux@...linux.org.uk>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 4/4] clk: mvebu: Expand mv98dx3236-core-clock support
On 07/02/17 12:14, Stephen Boyd wrote:
> On 02/03, Chris Packham wrote:
>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
>> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
>> Port code from the Marvell supplied Linux kernel to support different
>> PLL frequencies and provide clock gating support.
>>
>> Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
>> ---
>> .../devicetree/bindings/clock/mvebu-core-clock.txt | 7 +
>> .../bindings/clock/mvebu-gated-clock.txt | 11 ++
>> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 14 +-
>> drivers/clk/mvebu/Makefile | 2 +-
>> drivers/clk/mvebu/armada-xp.c | 13 --
>> drivers/clk/mvebu/mv98dx3236.c | 144 +++++++++++++++++++++
>
> This mixes dts and clk driver changes. Any chance it can be split
> up and just have the clk part go through clk tree? Otherwise, I
> can ack this if you want to take it all through arm-soc?
I'm happy to split it if it will make life easier.
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