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Message-ID: <201702070904.E8r8qYJg%fengguang.wu@intel.com>
Date: Tue, 7 Feb 2017 09:08:08 +0800
From: kbuild test robot <fengguang.wu@...el.com>
To: Ingo Molnar <mingo@...nel.org>
Cc: kbuild-all@...org, linux-kernel@...r.kernel.org, tipbuild@...or.com
Subject: [tip:WIP.sched/core 138/170]
arch/mips/paravirt/paravirt-smp.c:106:25: note: in expansion of macro
'__KSTK_TOS'
tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.sched/core
head: 4906e0da940c919f1669c365cb2e1434bd0cbbe9
commit: 239a7a08abab3068f29746f53d65c834c1c63579 [138/170] sched/headers: Split <linux/sched/task_stack> out of <linux/sched.h>
config: mips-mips_paravirt_defconfig (attached as .config)
compiler: mips64-linux-gnuabi64-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 239a7a08abab3068f29746f53d65c834c1c63579
# save the attached .config to linux build tree
make.cross ARCH=mips
All warnings (new ones prefixed by >>):
In file included from arch/mips/include/asm/thread_info.h:15:0,
from include/linux/thread_info.h:25,
from include/asm-generic/preempt.h:4,
from ./arch/mips/include/generated/asm/preempt.h:1,
from include/linux/preempt.h:80,
from include/linux/interrupt.h:8,
from arch/mips/paravirt/paravirt-smp.c:9:
arch/mips/paravirt/paravirt-smp.c: In function 'paravirt_boot_secondary':
arch/mips/include/asm/processor.h:384:41: error: implicit declaration of function 'task_stack_page' [-Werror=implicit-function-declaration]
#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + \
^
>> arch/mips/paravirt/paravirt-smp.c:106:25: note: in expansion of macro '__KSTK_TOS'
paravirt_smp_sp[cpu] = __KSTK_TOS(idle);
^~~~~~~~~~
cc1: some warnings being treated as errors
vim +/__KSTK_TOS +106 arch/mips/paravirt/paravirt-smp.c
18280eda David Daney 2014-05-28 3 * License. See the file "COPYING" in the main directory of this archive
18280eda David Daney 2014-05-28 4 * for more details.
18280eda David Daney 2014-05-28 5 *
18280eda David Daney 2014-05-28 6 * Copyright (C) 2013 Cavium, Inc.
18280eda David Daney 2014-05-28 7 */
18280eda David Daney 2014-05-28 8
18280eda David Daney 2014-05-28 @9 #include <linux/interrupt.h>
18280eda David Daney 2014-05-28 10 #include <linux/cpumask.h>
18280eda David Daney 2014-05-28 11 #include <linux/kernel.h>
18280eda David Daney 2014-05-28 12 #include <linux/sched.h>
18280eda David Daney 2014-05-28 13
18280eda David Daney 2014-05-28 14 #include <asm/mipsregs.h>
18280eda David Daney 2014-05-28 15 #include <asm/setup.h>
18280eda David Daney 2014-05-28 16 #include <asm/time.h>
18280eda David Daney 2014-05-28 17 #include <asm/smp.h>
18280eda David Daney 2014-05-28 18
18280eda David Daney 2014-05-28 19 /*
18280eda David Daney 2014-05-28 20 * Writing the sp releases the CPU, so writes must be ordered, gp
18280eda David Daney 2014-05-28 21 * first, then sp.
18280eda David Daney 2014-05-28 22 */
18280eda David Daney 2014-05-28 23 unsigned long paravirt_smp_sp[NR_CPUS];
18280eda David Daney 2014-05-28 24 unsigned long paravirt_smp_gp[NR_CPUS];
18280eda David Daney 2014-05-28 25
18280eda David Daney 2014-05-28 26 static int numcpus = 1;
18280eda David Daney 2014-05-28 27
18280eda David Daney 2014-05-28 28 static int __init set_numcpus(char *str)
18280eda David Daney 2014-05-28 29 {
18280eda David Daney 2014-05-28 30 int newval;
18280eda David Daney 2014-05-28 31
18280eda David Daney 2014-05-28 32 if (get_option(&str, &newval)) {
18280eda David Daney 2014-05-28 33 if (newval < 1 || newval >= NR_CPUS)
18280eda David Daney 2014-05-28 34 goto bad;
18280eda David Daney 2014-05-28 35 numcpus = newval;
18280eda David Daney 2014-05-28 36 return 0;
18280eda David Daney 2014-05-28 37 }
18280eda David Daney 2014-05-28 38 bad:
18280eda David Daney 2014-05-28 39 return -EINVAL;
18280eda David Daney 2014-05-28 40 }
18280eda David Daney 2014-05-28 41 early_param("numcpus", set_numcpus);
18280eda David Daney 2014-05-28 42
18280eda David Daney 2014-05-28 43
18280eda David Daney 2014-05-28 44 static void paravirt_smp_setup(void)
18280eda David Daney 2014-05-28 45 {
18280eda David Daney 2014-05-28 46 int id;
18280eda David Daney 2014-05-28 47 unsigned int cpunum = get_ebase_cpunum();
18280eda David Daney 2014-05-28 48
18280eda David Daney 2014-05-28 49 if (WARN_ON(cpunum >= NR_CPUS))
18280eda David Daney 2014-05-28 50 return;
18280eda David Daney 2014-05-28 51
18280eda David Daney 2014-05-28 52 /* The present CPUs are initially just the boot cpu (CPU 0). */
18280eda David Daney 2014-05-28 53 for (id = 0; id < NR_CPUS; id++) {
18280eda David Daney 2014-05-28 54 set_cpu_possible(id, id == 0);
18280eda David Daney 2014-05-28 55 set_cpu_present(id, id == 0);
18280eda David Daney 2014-05-28 56 }
18280eda David Daney 2014-05-28 57 __cpu_number_map[cpunum] = 0;
18280eda David Daney 2014-05-28 58 __cpu_logical_map[0] = cpunum;
18280eda David Daney 2014-05-28 59
18280eda David Daney 2014-05-28 60 for (id = 0; id < numcpus; id++) {
18280eda David Daney 2014-05-28 61 set_cpu_possible(id, true);
18280eda David Daney 2014-05-28 62 set_cpu_present(id, true);
18280eda David Daney 2014-05-28 63 __cpu_number_map[id] = id;
18280eda David Daney 2014-05-28 64 __cpu_logical_map[id] = id;
18280eda David Daney 2014-05-28 65 }
18280eda David Daney 2014-05-28 66 }
18280eda David Daney 2014-05-28 67
18280eda David Daney 2014-05-28 68 void irq_mbox_ipi(int cpu, unsigned int actions);
18280eda David Daney 2014-05-28 69 static void paravirt_send_ipi_single(int cpu, unsigned int action)
18280eda David Daney 2014-05-28 70 {
18280eda David Daney 2014-05-28 71 irq_mbox_ipi(cpu, action);
18280eda David Daney 2014-05-28 72 }
18280eda David Daney 2014-05-28 73
18280eda David Daney 2014-05-28 74 static void paravirt_send_ipi_mask(const struct cpumask *mask, unsigned int action)
18280eda David Daney 2014-05-28 75 {
18280eda David Daney 2014-05-28 76 unsigned int cpu;
18280eda David Daney 2014-05-28 77
8dd92891 Rusty Russell 2015-03-05 78 for_each_cpu(cpu, mask)
18280eda David Daney 2014-05-28 79 paravirt_send_ipi_single(cpu, action);
18280eda David Daney 2014-05-28 80 }
18280eda David Daney 2014-05-28 81
18280eda David Daney 2014-05-28 82 static void paravirt_init_secondary(void)
18280eda David Daney 2014-05-28 83 {
18280eda David Daney 2014-05-28 84 unsigned int sr;
18280eda David Daney 2014-05-28 85
18280eda David Daney 2014-05-28 86 sr = set_c0_status(ST0_BEV);
18280eda David Daney 2014-05-28 87 write_c0_ebase((u32)ebase);
18280eda David Daney 2014-05-28 88
18280eda David Daney 2014-05-28 89 sr |= STATUSF_IP2; /* Interrupt controller on IP2 */
18280eda David Daney 2014-05-28 90 write_c0_status(sr);
18280eda David Daney 2014-05-28 91
18280eda David Daney 2014-05-28 92 irq_cpu_online();
18280eda David Daney 2014-05-28 93 }
18280eda David Daney 2014-05-28 94
18280eda David Daney 2014-05-28 95 static void paravirt_smp_finish(void)
18280eda David Daney 2014-05-28 96 {
18280eda David Daney 2014-05-28 97 /* to generate the first CPU timer interrupt */
18280eda David Daney 2014-05-28 98 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
18280eda David Daney 2014-05-28 99 local_irq_enable();
18280eda David Daney 2014-05-28 100 }
18280eda David Daney 2014-05-28 101
18280eda David Daney 2014-05-28 102 static void paravirt_boot_secondary(int cpu, struct task_struct *idle)
18280eda David Daney 2014-05-28 103 {
18280eda David Daney 2014-05-28 104 paravirt_smp_gp[cpu] = (unsigned long)task_thread_info(idle);
18280eda David Daney 2014-05-28 105 smp_wmb();
18280eda David Daney 2014-05-28 @106 paravirt_smp_sp[cpu] = __KSTK_TOS(idle);
18280eda David Daney 2014-05-28 107 }
18280eda David Daney 2014-05-28 108
18280eda David Daney 2014-05-28 109 static irqreturn_t paravirt_reched_interrupt(int irq, void *dev_id)
:::::: The code at line 106 was first introduced by commit
:::::: 18280edafef1b8ffc920743eddaf6cf6612b1509 MIPS: Add code for new system 'paravirt'
:::::: TO: David Daney <david.daney@...ium.com>
:::::: CC: Ralf Baechle <ralf@...ux-mips.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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