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Date:   Tue, 7 Feb 2017 10:35:55 +0800
From:   cailiwei <cailiwei@...ilicon.com>
To:     <linux-fbdev@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <b.zolnierkie@...sung.com>, <guodong.xu@...aro.org>
CC:     <suzhuangluan@...ilicon.com>, <dengqingshan@...ilicon.com>,
        <xuhongtao8@...ilicon.com>, <zhengwanchun@...ilicon.com>,
        <shizongxuan@...wei.com>, <cailiwei@...ilicon.com>
Subject: [PATCH 4/8] fb: hisilicon: Add framebuffer driver for hi3660 SoC

From: Levy-Cai <cailiwei@...ilicon.com>

Add framebuffer driver for hi3660 SoC, this driver include lcd
driver & Hdmi adv7533/adv7535 driver, support lcd display at
1080p@60 and hdmi display at 1080p@60.

Signed-off-by: cailiwei <cailiwei@...ilicon.com>
---
 .../video/fbdev/hisi/dss/hisi_block_algorithm.c    |  714 +++++
 .../video/fbdev/hisi/dss/hisi_block_algorithm.h    |   29 +
 .../video/fbdev/hisi/dss/hisi_dpe_utils_hi3660.c   | 1549 ++++++++++
 drivers/video/fbdev/hisi/dss/hisi_dss.h            |  493 +++
 .../video/fbdev/hisi/dss/hisi_dss_regs_hi3660.h    | 3164 ++++++++++++++++++++
 5 files changed, 5949 insertions(+)
 create mode 100755 drivers/video/fbdev/hisi/dss/hisi_block_algorithm.c
 create mode 100755 drivers/video/fbdev/hisi/dss/hisi_block_algorithm.h
 create mode 100755 drivers/video/fbdev/hisi/dss/hisi_dpe_utils_hi3660.c
 create mode 100755 drivers/video/fbdev/hisi/dss/hisi_dss.h
 create mode 100755 drivers/video/fbdev/hisi/dss/hisi_dss_regs_hi3660.h

diff --git a/drivers/video/fbdev/hisi/dss/hisi_block_algorithm.c b/drivers/video/fbdev/hisi/dss/hisi_block_algorithm.c
new file mode 100755
index 000000000000..28dcfbd1fe13
--- /dev/null
+++ b/drivers/video/fbdev/hisi/dss/hisi_block_algorithm.c
@@ -0,0 +1,714 @@
+/*
+ * Copyright (c) 2013-2014, Hisilicon Tech. Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "hisi_fb.h"
+#include "hisi_block_algorithm.h"
+#include "hisi_overlay_utils.h"
+
+#define SCF_INPUT_OV  (16)
+
+#define WDMA_ROT_LINEBUF	(480)
+#define AFBCE_LINEBUF	(480)
+
+#define RCHN_V2_SCF_LINE_BUF (512)
+#define SHARPNESS_LINE_BUF	(2560)
+
+#define MAX_OFFLINE_SCF 4
+#define MAX_OFFLINE_LAYER_NUMBER 6
+#define BLOCK_SIZE_INVALID	(0xFFFF)
+
+int rect_across_rect(dss_rect_t rect1, dss_rect_t rect2,
+		     dss_rect_t *cross_rect)
+{
+	uint32_t center_x = 0;
+	uint32_t center_y = 0;
+
+	BUG_ON(cross_rect == NULL);
+
+	memset(cross_rect, 0x0, sizeof(dss_rect_t));
+
+	if (rect1.w == 0 || rect1.h == 0 || rect2.w == 0 || rect2.h == 0)
+		return 0;
+
+	center_x =
+	    abs(rect2.x + rect2.w - 1 + rect2.x -
+		(rect1.x + rect1.w - 1 + rect1.x));
+	center_y =
+	    abs(rect2.y + rect2.h - 1 + rect2.y -
+		(rect1.y + rect1.h - 1 + rect1.y));
+
+	if ((center_x < rect2.w + rect1.w) && (center_y < rect2.h + rect1.h)) {
+
+		cross_rect->x = MAX(rect1.x, rect2.x);
+		cross_rect->y = MAX(rect1.y, rect2.y);
+		cross_rect->w =
+		    MIN(rect1.x + rect1.w - 1,
+			rect2.x + rect2.w - 1) - cross_rect->x + 1;
+		cross_rect->h =
+		    MIN(rect1.y + rect1.h - 1,
+			rect2.y + rect2.h - 1) - cross_rect->y + 1;
+
+		return 1;
+	}
+
+	return 0;
+}
+
+uint32_t calc_dest_block_size(dss_overlay_t *pov_req,
+			      dss_overlay_block_t *pov_h_block)
+{
+	uint32_t i = 0;
+	uint32_t block_width = BLOCK_SIZE_INVALID;
+	int32_t scf_line_buffer = SCF_LINE_BUF;
+	dss_layer_t *layer = NULL;
+	dss_wb_layer_t *wb_layer = NULL;
+
+	BUG_ON(pov_req == NULL);
+	BUG_ON(pov_h_block == NULL);
+
+	for (i = 0; i < pov_h_block->layer_nums; i++) {
+		layer = &(pov_h_block->layer_infos[i]);
+
+		if (layer->need_cap & (CAP_DIM | CAP_BASE))
+			continue;
+
+		/* sharpenss line buffer is 1600 for austin and dallas, but 2560 for chicago */
+		if ((layer->need_cap & CAP_2D_SHARPNESS) &&
+		    (layer->src_rect.w > SHARPNESS_LINE_BUF)) {
+			block_width = MIN(block_width, SHARPNESS_LINE_BUF);
+		}
+
+		/* scaler line buffer, default value is 2560, but line buffer of rchn_v2 is 512,
+		   scaler line buffer should be subtracted by 32 according to scale algorithm */
+		if (layer->chn_idx == DSS_RCHN_V2) {
+			scf_line_buffer = RCHN_V2_SCF_LINE_BUF;
+		} else {
+			scf_line_buffer = SCF_LINE_BUF;
+		}
+
+		scf_line_buffer = scf_line_buffer - 32;
+
+		if (layer->src_rect.h != layer->dst_rect.h) {
+			if (((layer->src_rect.w >= layer->dst_rect.w)
+			     && (layer->dst_rect.w > scf_line_buffer))
+			    || ((layer->src_rect.w < layer->dst_rect.w)
+				&& (layer->src_rect.w > scf_line_buffer))) {
+				block_width = MIN(block_width, scf_line_buffer);
+			}
+		}
+	}
+
+	for (i = 0; i < pov_req->wb_layer_nums; i++) {
+		wb_layer = &(pov_req->wb_layer_infos[i]);
+
+		/* maximum of rot linebuffer is 480 */
+		if (wb_layer->transform & HISI_FB_TRANSFORM_ROT_90) {
+			block_width = MIN(block_width, WDMA_ROT_LINEBUF);
+		}
+
+		/* maximum of afbce linebuffer is 480 */
+		if (wb_layer->need_cap & CAP_AFBCE) {
+			block_width = MIN(block_width, AFBCE_LINEBUF);
+		}
+	}
+
+	return block_width;
+}
+
+int scf_output_suitable(uint32_t x_start, uint32_t x_end, uint32_t pos)
+{
+	if ((x_start > pos) || (x_end < pos))
+		return 0;
+
+	/* if distance between layer start/end and pos, return 1 for adjust */
+	if ((pos - x_start < SCF_MIN_OUTPUT)
+	    || (x_end - pos + 1 < SCF_MIN_OUTPUT))
+		return 1;
+
+	return 0;
+}
+
+int block_fix_scf_constraint(dss_overlay_t *pov_req,
+			     dss_overlay_block_t *pov_h_block,
+			     uint32_t block_size, uint32_t end_pos,
+			     uint32_t *fix_size)
+{
+	uint32_t i = 0;
+	uint32_t end = end_pos;
+	uint32_t scf_layer_num = 0;
+
+	dss_rect_t scf_dst_rect[MAX_OFFLINE_LAYER_NUMBER];
+	dss_layer_t *layer = NULL;
+
+	BUG_ON(pov_h_block == NULL);
+	BUG_ON(fix_size == NULL);
+
+	*fix_size = block_size;
+
+	if (block_size <= SCF_MIN_OUTPUT) {
+		HISI_FB_ERR("block size[%d] is too small!\n", block_size);
+		return -1;
+	}
+
+	for (i = 0; i < pov_h_block->layer_nums; i++) {
+		layer = &(pov_h_block->layer_infos[i]);
+
+		if (layer->need_cap & (CAP_BASE | CAP_DIM | CAP_PURE_COLOR)) {
+			continue;
+		}
+
+		if (scf_layer_num >= MAX_OFFLINE_LAYER_NUMBER) {
+			HISI_FB_ERR
+			    ("layer number in offline [%d] is more than scf moudle [%d]\n",
+			     scf_layer_num, MAX_OFFLINE_LAYER_NUMBER);
+			return -1;
+		}
+
+		/* get all scaler layers for austin and dallas */
+		/* get all layers for chicago */
+		scf_dst_rect[scf_layer_num].x = layer->dst_rect.x;
+		scf_dst_rect[scf_layer_num].y = layer->dst_rect.y;
+		scf_dst_rect[scf_layer_num].w = layer->dst_rect.w;
+		scf_dst_rect[scf_layer_num].h = layer->dst_rect.h;
+		scf_layer_num++;
+	}
+
+	if (scf_layer_num == 0)
+		return 0;
+
+ REDO:
+	for (i = 0; i < scf_layer_num; i++) {
+		if (scf_output_suitable(scf_dst_rect[i].x,
+					scf_dst_rect[i].x + scf_dst_rect[i].w -
+					1, pov_req->wb_ov_rect.x + end)) {
+			end = end - SCF_MIN_OUTPUT;
+			goto REDO;
+		}
+	}
+
+	*fix_size = block_size - (end_pos - end);
+	return 0;
+}
+
+int adjust_layers_cap(dss_overlay_t *pov_req,
+		      dss_overlay_block_t *pov_h_block,
+		      dss_wb_layer_t *wb_layer)
+{
+	int i = 0;
+	int temp = 0;
+	dss_layer_t *layer = NULL;
+	bool has_rot = false;
+
+	BUG_ON(pov_h_block == NULL);
+	BUG_ON(wb_layer == NULL);
+
+	for (i = 0; i < pov_h_block->layer_nums; i++) {
+		layer = &pov_h_block->layer_infos[i];
+
+		if (layer->transform & HISI_FB_TRANSFORM_ROT_90) {
+			temp = layer->dst_rect.x;
+			layer->dst_rect.x =
+			    pov_req->wb_ov_rect.x + (layer->dst_rect.y -
+						     pov_req->wb_ov_rect.y);
+			layer->dst_rect.y =
+			    pov_req->wb_ov_rect.y + temp -
+			    pov_req->wb_ov_rect.x;
+
+			temp = layer->dst_rect.w;
+			layer->dst_rect.w = layer->dst_rect.h;
+			layer->dst_rect.h = temp;
+
+			if (layer->transform == HISI_FB_TRANSFORM_ROT_90) {
+				layer->transform = HISI_FB_TRANSFORM_FLIP_V;
+
+			} else if (layer->transform ==
+				   HISI_FB_TRANSFORM_ROT_270) {
+				layer->transform = HISI_FB_TRANSFORM_FLIP_H;
+
+			} else if (layer->transform ==
+				   (HISI_FB_TRANSFORM_ROT_90 |
+				    HISI_FB_TRANSFORM_FLIP_H)) {
+				layer->transform = HISI_FB_TRANSFORM_ROT_180;
+
+			} else if (layer->transform ==
+				   (HISI_FB_TRANSFORM_ROT_90 |
+				    HISI_FB_TRANSFORM_FLIP_V)) {
+				layer->transform = HISI_FB_TRANSFORM_NOP;
+
+			} else {
+				;
+			}
+
+			has_rot = true;
+		}
+	}
+
+
+	if (has_rot) {
+		for (i = 0; i < pov_req->wb_layer_nums; i++) {
+			wb_layer = &(pov_req->wb_layer_infos[i]);
+			temp = wb_layer->src_rect.w;
+			wb_layer->src_rect.w = wb_layer->src_rect.h;
+			wb_layer->src_rect.h = temp;
+
+			wb_layer->transform =
+			    (HISI_FB_TRANSFORM_ROT_90 |
+			     HISI_FB_TRANSFORM_FLIP_V);
+		}
+	}
+
+	return 0;
+}
+
+int get_ov_block_rect(dss_overlay_t *pov_req,
+		      dss_overlay_block_t *pov_h_block,
+		      dss_wb_layer_t *wb_layer, int *block_num,
+		      dss_rect_t *ov_block_rects[])
+{
+	int ret = 0;
+	uint32_t block_size = 0xFFFF;
+	uint32_t current_offset = 0;
+	uint32_t last_offset = 0;
+	uint32_t fix_scf_span = 0;
+	dss_layer_t *layer = NULL;
+	uint32_t i = 0;
+	int block_has_layer = 0;
+	int w = 0;
+	int h = 0;
+
+	BUG_ON(pov_req == NULL);
+	BUG_ON(pov_h_block == NULL);
+	BUG_ON(ov_block_rects == NULL);
+	BUG_ON(block_num == NULL);
+	BUG_ON(wb_layer == NULL);
+
+	*block_num = 0;
+
+	/* adjust layer transform cap, source layer dst_rect and writeback layer src_rect */
+	adjust_layers_cap(pov_req, pov_h_block, wb_layer);
+	w = wb_layer->src_rect.w;
+	h = wb_layer->src_rect.h;
+
+	/* init block size according to source layer dst_rect */
+	block_size = calc_dest_block_size(pov_req, pov_h_block);
+
+	/* if block size is invalid or larger than write back width, block is not needed.
+	   Then block num is set to 1, and block rect is set to write back layer rect */
+	if ((block_size == BLOCK_SIZE_INVALID) || (block_size >= w)) {
+		ov_block_rects[*block_num]->x = wb_layer->src_rect.x;
+		ov_block_rects[*block_num]->y = wb_layer->src_rect.y;
+		ov_block_rects[*block_num]->w = wb_layer->src_rect.w;
+		ov_block_rects[*block_num]->h = wb_layer->src_rect.h;
+
+		*block_num = 1;
+		return ret;
+	}
+
+	current_offset = block_size;
+	fix_scf_span = block_size;
+
+	for (current_offset = block_size; last_offset < w;
+	     last_offset = current_offset, current_offset += block_size) {
+		/* make sure each block of scaler layer is larger than 16 */
+		if (block_fix_scf_constraint
+		    (pov_req, pov_h_block, block_size, current_offset,
+		     &fix_scf_span) != 0) {
+			HISI_FB_ERR("block_fix_scf_constraint err!\n");
+			return -3;
+		}
+
+		/* recalculate the block size, the final value */
+		current_offset = current_offset - (block_size - fix_scf_span);
+		block_has_layer = 0;
+
+		for (i = 0; i < pov_h_block->layer_nums; i++) {
+			layer = &(pov_h_block->layer_infos[i]);
+
+			if (((last_offset + pov_req->wb_ov_rect.x) <=
+			     (layer->dst_rect.x + layer->dst_rect.w - 1))
+			    && (layer->dst_rect.x <
+				(current_offset + pov_req->wb_ov_rect.x))) {
+				block_has_layer = 1;
+				if ((*block_num) >= HISI_DSS_OFFLINE_MAX_BLOCK)
+					return -5;
+
+				/* get the block rectangles */
+				ov_block_rects[*block_num]->x =
+				    wb_layer->src_rect.x + last_offset;
+				ov_block_rects[*block_num]->y =
+				    wb_layer->src_rect.y;
+				ov_block_rects[*block_num]->w =
+				    MIN(current_offset - last_offset,
+					w - last_offset);
+				ov_block_rects[*block_num]->h = h;
+
+				(*block_num)++;
+				break;
+			}
+		}
+
+		if (block_has_layer == 0) {
+			if ((*block_num) >= HISI_DSS_OFFLINE_MAX_BLOCK)
+				return -6;
+
+			ov_block_rects[*block_num]->x =
+			    wb_layer->src_rect.x + last_offset;
+			ov_block_rects[*block_num]->y = wb_layer->src_rect.y;
+			ov_block_rects[*block_num]->w =
+			    MIN(current_offset - last_offset, w - last_offset);
+			ov_block_rects[*block_num]->h = h;
+
+			(*block_num)++;
+		}
+
+		if (g_debug_ovl_block_composer) {
+			HISI_FB_INFO
+			    ("ov_block_rects[%d]:[%d:%d:%d:%d], current_offset=%d, "
+			     "fix_scf_span=%d, last_offset=%d, w=%d!\n",
+			     *block_num, ov_block_rects[*block_num - 1]->x,
+			     ov_block_rects[*block_num - 1]->y,
+			     ov_block_rects[*block_num - 1]->w,
+			     ov_block_rects[*block_num - 1]->h, current_offset,
+			     fix_scf_span, last_offset, w);
+		}
+	}
+
+	hisifb_adjust_block_rect(*block_num, ov_block_rects, wb_layer);
+
+	return ret;
+}
+
+static int create_h_v_block_layer(dss_layer_t *h_layer,
+				  dss_layer_t *h_v_layer,
+				  dss_rect_t dst_cross_rect,
+				  dss_rect_t ov_block_rect)
+{
+	int input_startpos = 0;
+	int input_span = 0;
+	uint32_t output_startpos = 0;
+	uint32_t output_span = 0;
+	int h_ratio = 0;
+	int acc_hscl = 0;
+	int scf_read_start = 0;
+	int scf_read_end = 0;
+	dss_rect_t rect_transform = { 0 };
+	dss_rect_t src_rect = { 0 };
+	int scf_int = 0;
+	int scf_rem = 0;
+
+	dss_rect_t dst_rect = { 0 };
+	int first_block = 0;
+	int last_block = 0;
+	int scf_in_start = 0;
+	int scf_in_end = 0;
+
+	BUG_ON(h_layer == NULL);
+	BUG_ON(h_v_layer == NULL);
+
+	first_block = (h_layer->dst_rect.x >= ov_block_rect.x) ? 1 : 0;
+	last_block =
+	    ((ov_block_rect.x + ov_block_rect.w) >=
+	     (h_layer->dst_rect.x + h_layer->dst_rect.w)) ? 1 : 0;
+
+	output_startpos = dst_cross_rect.x - h_layer->dst_rect.x;
+	output_span = dst_cross_rect.w;
+	input_startpos = output_startpos;
+	input_span = output_span;
+
+	/* handle arsr2p layer */
+#define ARSR2P_OVERLAPH 16
+
+	if (h_layer->chn_idx == DSS_RCHN_V0
+	    && (h_layer->src_rect.w < h_layer->dst_rect.w
+		|| h_layer->src_rect.h != h_layer->dst_rect.h
+		|| (h_layer->need_cap & CAP_2D_SHARPNESS))) {
+
+		if ((!first_block) && (output_startpos % 2)) {
+			h_v_layer->block_info.arsr2p_left_clip = 1;
+			dst_cross_rect.x =
+			    dst_cross_rect.x -
+			    h_v_layer->block_info.arsr2p_left_clip;
+			dst_cross_rect.w =
+			    dst_cross_rect.w +
+			    h_v_layer->block_info.arsr2p_left_clip;
+
+			output_startpos =
+			    output_startpos -
+			    h_v_layer->block_info.arsr2p_left_clip;
+			output_span = dst_cross_rect.w;
+			input_startpos = output_startpos;
+			input_span = output_span;
+		}
+
+		if (h_layer->src_rect.w > h_layer->dst_rect.w) {
+			src_rect.x = h_layer->src_rect.x;
+			src_rect.y = h_layer->src_rect.y;
+			src_rect.w = h_layer->dst_rect.w;
+			src_rect.h = h_layer->src_rect.h;
+		} else {
+			src_rect = h_layer->src_rect;
+		}
+
+		h_ratio =
+		    (DSS_WIDTH(src_rect.w) * ARSR2P_INC_FACTOR +
+		     ARSR2P_INC_FACTOR - acc_hscl) / h_layer->dst_rect.w;
+
+		scf_int = output_startpos * h_ratio / ARSR2P_INC_FACTOR;
+		scf_rem = output_startpos * h_ratio % ARSR2P_INC_FACTOR;
+		scf_in_start = (scf_rem > 0) ? (scf_int + 1) : scf_int;
+
+		scf_int =
+		    (output_startpos +
+		     output_span) * h_ratio / ARSR2P_INC_FACTOR;
+		scf_rem =
+		    (output_startpos +
+		     output_span) * h_ratio % ARSR2P_INC_FACTOR;
+		scf_in_end = (scf_rem > 0) ? (scf_int + 1) : scf_int;
+
+		if ((first_block == 1) && (last_block == 1)) {
+			scf_read_start = 0;
+			scf_read_end = DSS_WIDTH(src_rect.w);
+			h_v_layer->block_info.last_tile = 1;
+		} else if (first_block == 1) {
+			scf_read_start = 0;
+			scf_read_end = scf_in_end + ARSR2P_OVERLAPH - 1;
+		} else {
+			scf_read_start = scf_in_start - ARSR2P_OVERLAPH;
+			if (scf_read_start < 0)
+				scf_read_start = 0;
+
+			if (last_block == 1) {
+				scf_read_end = DSS_WIDTH(src_rect.w);
+				h_v_layer->block_info.last_tile = 1;
+			} else {
+				scf_read_end = scf_in_end + ARSR2P_OVERLAPH - 1;
+			}
+		}
+
+		if (scf_read_end > DSS_WIDTH(src_rect.w))
+			scf_read_end = DSS_WIDTH(src_rect.w);
+
+		input_startpos = scf_read_start;
+		input_span = scf_read_end - scf_read_start + 1;
+		h_v_layer->block_info.h_ratio_arsr2p = h_ratio;
+		h_v_layer->block_info.arsr2p_src_x = h_layer->src_rect.x;
+		h_v_layer->block_info.arsr2p_src_y = h_layer->src_rect.y;
+		h_v_layer->block_info.arsr2p_dst_x = h_layer->dst_rect.x;
+		h_v_layer->block_info.arsr2p_dst_y = h_layer->dst_rect.y;
+		h_v_layer->block_info.arsr2p_dst_w = h_layer->dst_rect.w;
+
+		rect_transform.x = h_layer->src_rect.x + input_startpos;
+		rect_transform.y = h_layer->src_rect.y;
+		rect_transform.w = input_span;
+		rect_transform.h = h_layer->src_rect.h;
+		h_v_layer->block_info.arsr2p_in_rect = rect_transform;
+		h_v_layer->src_rect = rect_transform;
+		rect_across_rect(h_v_layer->src_rect, h_v_layer->src_rect_mask,
+				 &h_v_layer->src_rect_mask);
+		h_v_layer->dst_rect = dst_cross_rect;
+	}
+	/* scaling not in rchn v0 or scaling down in rchn v0 */
+	if (((h_layer->src_rect.w != h_layer->dst_rect.w)
+	     && (h_layer->chn_idx != DSS_RCHN_V0))
+	    || ((h_layer->src_rect.w > h_layer->dst_rect.w)
+		 && (h_layer->chn_idx == DSS_RCHN_V0))) {
+		/* check if arsr2p input has already extened width */
+		if (h_v_layer->block_info.h_ratio_arsr2p) {
+			dst_rect = rect_transform;
+			h_v_layer->block_info.both_vscfh_arsr2p_used = 1;
+			output_startpos = input_startpos;
+			output_span = dst_rect.w;
+			input_startpos = output_startpos;
+			input_span = output_span;
+		} else {
+			dst_rect = h_layer->dst_rect;
+		}
+
+		h_ratio =
+		    (DSS_WIDTH(h_layer->src_rect.w) * SCF_INC_FACTOR +
+		     SCF_INC_FACTOR / 2 -
+		     acc_hscl) / DSS_WIDTH(h_layer->dst_rect.w);
+
+		scf_in_start = output_startpos * h_ratio / SCF_INC_FACTOR;
+		scf_in_end =
+		    DSS_WIDTH(output_startpos +
+			      output_span) * h_ratio / SCF_INC_FACTOR;
+
+		if ((first_block == 1) && (last_block == 1)) {
+			acc_hscl = 0;
+			scf_read_start = 0;
+			scf_read_end = DSS_WIDTH(h_layer->src_rect.w);
+		} else if (first_block == 1) {
+			acc_hscl = 0;
+			scf_read_start = 0;
+			scf_read_end = scf_in_end + SCF_INPUT_OV;
+		} else {
+			scf_read_start = scf_in_start - SCF_INPUT_OV;
+			if (scf_read_start < 0)
+				scf_read_start = 0;
+			acc_hscl =
+			    output_startpos * h_ratio -
+			    scf_read_start * SCF_INC_FACTOR;
+
+			if (last_block == 1) {
+				scf_read_end = DSS_WIDTH(h_layer->src_rect.w);
+			} else {
+				scf_read_end = scf_in_end + SCF_INPUT_OV;
+			}
+		}
+
+		if (scf_read_end > DSS_WIDTH(h_layer->src_rect.w))
+			scf_read_end = DSS_WIDTH(h_layer->src_rect.w);
+
+		input_startpos = scf_read_start;
+		input_span = scf_read_end - scf_read_start + 1;
+		h_v_layer->block_info.h_ratio = h_ratio;
+		h_v_layer->block_info.acc_hscl = acc_hscl;
+
+		if (g_debug_ovl_block_composer) {
+			HISI_FB_INFO
+			    ("first_block=%d, last_block=%d, output_startpos=%d, output_span=%d, "
+			     "h_ratio=%d, acc_hscl=%d, scf_read_start=%d,"
+			     "scf_read_end=%d, input_startpos=%d, input_span=%d\n",
+			     first_block, last_block, output_startpos,
+			     output_span, h_ratio, acc_hscl, scf_read_start,
+			     scf_read_end, input_startpos, input_span);
+		}
+	}
+
+	switch (h_v_layer->transform) {
+	case HISI_FB_TRANSFORM_NOP:
+	case HISI_FB_TRANSFORM_FLIP_V:
+		rect_transform.x = h_layer->src_rect.x + input_startpos;
+		rect_transform.y = h_layer->src_rect.y;
+		rect_transform.w = input_span;
+		rect_transform.h = h_layer->src_rect.h;
+		break;
+	case HISI_FB_TRANSFORM_ROT_180:
+	case HISI_FB_TRANSFORM_FLIP_H:
+		rect_transform.x =
+		    h_layer->src_rect.x + h_layer->src_rect.w - input_startpos -
+		    input_span;
+		rect_transform.y = h_layer->src_rect.y;
+		rect_transform.w = input_span;
+		rect_transform.h = h_layer->src_rect.h;
+		break;
+	default:
+		HISI_FB_ERR("unknown h_v_layer->transform=%d!\n",
+			    h_v_layer->transform);
+		return -EINVAL;
+	}
+
+	h_v_layer->src_rect = rect_transform;
+	rect_across_rect(h_v_layer->src_rect, h_v_layer->src_rect_mask,
+			 &h_v_layer->src_rect_mask);
+
+	if (!h_v_layer->block_info.both_vscfh_arsr2p_used)
+		h_v_layer->dst_rect = dst_cross_rect;
+
+	return 0;
+}
+
+int get_block_layers(dss_overlay_t *pov_req, dss_overlay_block_t *pov_h_block,
+		     dss_rect_t ov_block_rect, dss_overlay_t *pov_req_h_v)
+{
+	uint32_t i = 0;
+	int ret = 0;
+	dss_rect_t dst_cross_rect;
+	dss_rect_t wb_ov_rect;
+	dss_overlay_block_t *pov_h_v_block = NULL;
+	dss_layer_t *h_layer = NULL;
+	dss_layer_t *h_v_layer = NULL;
+	int h_v_layer_idx = 0;
+
+	BUG_ON(pov_req == NULL);
+	BUG_ON(pov_h_block == NULL);
+	BUG_ON(pov_req_h_v == NULL);
+
+	if (!ov_block_rect.w || !ov_block_rect.h) {
+		HISI_FB_ERR("invaild args, ov_block_rect(%d,%d,%d,%d)!\n",
+			    ov_block_rect.x, ov_block_rect.y, ov_block_rect.w,
+			    ov_block_rect.y);
+		return -1;
+	}
+
+	pov_h_v_block = (dss_overlay_block_t *) pov_req_h_v->ov_block_infos_ptr;
+	memcpy(pov_req_h_v, pov_req, sizeof(dss_overlay_t));
+	pov_req_h_v->ov_block_infos_ptr = (uint64_t) (pov_h_v_block);
+
+	if (calc_dest_block_size(pov_req, pov_h_block) == BLOCK_SIZE_INVALID) {
+		pov_req_h_v->ov_block_nums = 1;
+		memcpy(pov_h_v_block, pov_h_block, sizeof(dss_overlay_block_t));
+		return 0;
+	}
+
+	pov_h_v_block->layer_nums = 0;
+	h_v_layer_idx = 0;
+	memcpy(&pov_h_v_block->ov_block_rect, &pov_h_block->ov_block_rect,
+	       sizeof(dss_rect_t));
+	wb_ov_rect.x = pov_req->wb_ov_rect.x + ov_block_rect.x;
+	wb_ov_rect.y = pov_req->wb_ov_rect.y;
+	wb_ov_rect.w = ov_block_rect.w;
+	wb_ov_rect.h = ov_block_rect.h;
+
+	for (i = 0; i < pov_h_block->layer_nums; i++) {
+		h_layer = &(pov_h_block->layer_infos[i]);
+
+		ret =
+		    rect_across_rect(h_layer->dst_rect, wb_ov_rect,
+				     &dst_cross_rect);
+		if (ret == 0)
+			continue;
+
+		h_v_layer = &(pov_h_v_block->layer_infos[h_v_layer_idx]);
+		memcpy(h_v_layer, h_layer, sizeof(dss_layer_t));
+		h_v_layer->layer_idx = h_v_layer_idx;
+
+		ret =
+		    create_h_v_block_layer(h_layer, h_v_layer, dst_cross_rect,
+					   wb_ov_rect);
+		if ((ret != 0) || g_debug_ovl_block_composer) {
+			HISI_FB_INFO
+			    ("h_layer[%d](transform[%d], wb_ov_rect[%d,%d,%d,%d], "
+			     "src_rect[%d,%d,%d,%d], dst_rect[%d,%d,%d,%d]), "
+			     "h_v_layer[%d](transform[%d], src_rect[%d,%d,%d,%d], "
+			     "dst_rect[%d,%d,%d,%d], dst_cross_rect[%d,%d,%d,%d])\n",
+			     i, h_layer->transform, wb_ov_rect.x, wb_ov_rect.y,
+			     wb_ov_rect.w, wb_ov_rect.h, h_layer->src_rect.x,
+			     h_layer->src_rect.y, h_layer->src_rect.w,
+			     h_layer->src_rect.h, h_layer->dst_rect.x,
+			     h_layer->dst_rect.y, h_layer->dst_rect.w,
+			     h_layer->dst_rect.h, h_v_layer_idx,
+			     h_v_layer->transform, h_v_layer->src_rect.x,
+			     h_v_layer->src_rect.y, h_v_layer->src_rect.w,
+			     h_v_layer->src_rect.h, h_v_layer->dst_rect.x,
+			     h_v_layer->dst_rect.y, h_v_layer->dst_rect.w,
+			     h_v_layer->dst_rect.h, dst_cross_rect.x,
+			     dst_cross_rect.y, dst_cross_rect.w,
+			     dst_cross_rect.h);
+		}
+
+		if (ret != 0) {
+			HISI_FB_ERR
+			    ("create_h_v_block_layer failed, h_layer[%d], h_v_layer[%d]!\n",
+			     i, h_v_layer_idx);
+			break;
+		}
+
+		h_v_layer_idx++;
+		pov_h_v_block->layer_nums = h_v_layer_idx;
+	}
+
+	return ret;
+}
diff --git a/drivers/video/fbdev/hisi/dss/hisi_block_algorithm.h b/drivers/video/fbdev/hisi/dss/hisi_block_algorithm.h
new file mode 100755
index 000000000000..dcbd01650814
--- /dev/null
+++ b/drivers/video/fbdev/hisi/dss/hisi_block_algorithm.h
@@ -0,0 +1,29 @@
+/* Copyright (c) 2013-2014, Hisilicon Tech. Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __HISI_BLOCK_ALGORITHM_H__
+#define __HISI_BLOCK_ALGORITHM_H__
+
+#include "hisi_dss.h"
+
+int get_ov_block_rect(dss_overlay_t *pov_req_h,
+		      dss_overlay_block_t *pov_h_block,
+		      dss_wb_layer_t *wb_layer, int *block_num,
+		      dss_rect_t *ov_block_rects[]);
+int get_block_layers(dss_overlay_t *pov_req_h,
+		     dss_overlay_block_t *pov_h_block,
+		     dss_rect_t ov_block_rect, dss_overlay_t *pov_req_v_block);
+int rect_across_rect(dss_rect_t rect1, dss_rect_t rect2,
+		     dss_rect_t *cross_rect);
+
+#endif
diff --git a/drivers/video/fbdev/hisi/dss/hisi_dpe_utils_hi3660.c b/drivers/video/fbdev/hisi/dss/hisi_dpe_utils_hi3660.c
new file mode 100755
index 000000000000..87b9768de329
--- /dev/null
+++ b/drivers/video/fbdev/hisi/dss/hisi_dpe_utils_hi3660.c
@@ -0,0 +1,1549 @@
+/* Copyright (c) 2013-2014, Hisilicon Tech. Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include "hisi_dpe_utils.h"
+
+DEFINE_SEMAPHORE(hisi_fb_dss_inner_clk_sem);
+
+static int dss_inner_clk_refcount = 0;
+
+#define OFFSET_FRACTIONAL_BITS	(11)
+#define ROUND1(x,y)	((x) / (y) + ((x) % (y)  ? 1 : 0))
+
+static int get_lcd_frame_rate(struct hisi_panel_info *pinfo)
+{
+	return pinfo->pxl_clk_rate / (pinfo->xres + pinfo->pxl_clk_rate_div *
+				      (pinfo->ldi.h_back_porch +
+				       pinfo->ldi.h_front_porch +
+				       pinfo->ldi.h_pulse_width)) /
+	    (pinfo->yres + pinfo->ldi.v_back_porch + pinfo->ldi.v_front_porch +
+	     pinfo->ldi.v_pulse_width);
+}
+
+struct dss_clk_rate *get_dss_clk_rate(struct hisi_fb_data_type *hisifd)
+{
+	struct hisi_panel_info *pinfo = NULL;
+	struct dss_clk_rate *pdss_clk_rate = NULL;
+	int frame_rate = 0;
+
+	BUG_ON(hisifd == NULL);
+
+	pinfo = &(hisifd->panel_info);
+	pdss_clk_rate = &(hisifd->dss_clk_rate);
+	frame_rate = get_lcd_frame_rate(pinfo);
+
+	if (pdss_clk_rate->dss_pclk_dss_rate == 0) {
+		if ((pinfo->xres * pinfo->yres) >= (RES_4K_PHONE)) {
+			pdss_clk_rate->dss_pri_clk_rate =
+			    DEFAULT_DSS_CORE_CLK_08V_RATE;
+			pdss_clk_rate->dss_pclk_dss_rate =
+			    DEFAULT_PCLK_DSS_RATE;
+			pdss_clk_rate->dss_pclk_pctrl_rate =
+			    DEFAULT_PCLK_PCTRL_RATE;
+			hisifd->core_clk_upt_support = 0;
+
+		} else if ((pinfo->xres * pinfo->yres) >= (RES_1440P)) {
+			if (frame_rate >= 110) {
+				pdss_clk_rate->dss_pri_clk_rate =
+				    DEFAULT_DSS_CORE_CLK_08V_RATE;
+				pdss_clk_rate->dss_pclk_dss_rate =
+				    DEFAULT_PCLK_DSS_RATE;
+				pdss_clk_rate->dss_pclk_pctrl_rate =
+				    DEFAULT_PCLK_PCTRL_RATE;
+				hisifd->core_clk_upt_support = 0;
+			} else {
+				pdss_clk_rate->dss_pri_clk_rate =
+				    DEFAULT_DSS_CORE_CLK_07V_RATE;
+				pdss_clk_rate->dss_pclk_dss_rate =
+				    DEFAULT_PCLK_DSS_RATE;
+				pdss_clk_rate->dss_pclk_pctrl_rate =
+				    DEFAULT_PCLK_PCTRL_RATE;
+				hisifd->core_clk_upt_support = 1;
+			}
+
+		} else if ((pinfo->xres * pinfo->yres) >= (RES_1080P)) {
+			pdss_clk_rate->dss_pri_clk_rate =
+			    DEFAULT_DSS_CORE_CLK_07V_RATE;
+			pdss_clk_rate->dss_pclk_dss_rate =
+			    DEFAULT_PCLK_DSS_RATE;
+			pdss_clk_rate->dss_pclk_pctrl_rate =
+			    DEFAULT_PCLK_PCTRL_RATE;
+			hisifd->core_clk_upt_support = 1;
+
+		} else {
+			pdss_clk_rate->dss_pri_clk_rate =
+			    DEFAULT_DSS_CORE_CLK_07V_RATE;
+			pdss_clk_rate->dss_pclk_dss_rate =
+			    DEFAULT_PCLK_DSS_RATE;
+			pdss_clk_rate->dss_pclk_pctrl_rate =
+			    DEFAULT_PCLK_PCTRL_RATE;
+			hisifd->core_clk_upt_support = 1;
+		}
+	}
+
+	return pdss_clk_rate;
+}
+
+int set_dss_clk_rate(struct hisi_fb_data_type *hisifd,
+		     dss_clk_rate_t dss_clk_rate)
+{
+	int ret = 0;
+
+	if (NULL == hisifd) {
+		HISI_FB_ERR("NULL Pointer!\n");
+		return -1;
+	}
+
+	if ((dss_clk_rate.dss_pri_clk_rate != DEFAULT_DSS_CORE_CLK_08V_RATE)
+	    && (dss_clk_rate.dss_pri_clk_rate != DEFAULT_DSS_CORE_CLK_07V_RATE)) {
+		HISI_FB_ERR("no support set dss_pri_clk_rate(%llu)!\n",
+			    dss_clk_rate.dss_pri_clk_rate);
+		return -1;
+	}
+
+	if (dss_clk_rate.dss_pri_clk_rate ==
+	    hisifd->dss_clk_rate.dss_pri_clk_rate) {
+		return ret;
+	}
+
+	ret = clk_set_rate(hisifd->dss_pri_clk, dss_clk_rate.dss_pri_clk_rate);
+	if (ret < 0) {
+		HISI_FB_ERR("set dss_pri_clk_rate(%llu) failed, error=%d!\n",
+			    dss_clk_rate.dss_pri_clk_rate, ret);
+		return -1;
+	}
+
+	hisifd->dss_clk_rate.dss_pri_clk_rate = dss_clk_rate.dss_pri_clk_rate;
+
+	return ret;
+}
+
+void dss_inner_clk_common_enable(struct hisi_fb_data_type *hisifd,
+				 bool fastboot_enable)
+{
+	char __iomem *dss_base = NULL;
+	int prev_refcount = 0;
+
+	BUG_ON(hisifd == NULL);
+
+	dss_base = hisifd->dss_base;
+
+	down(&hisi_fb_dss_inner_clk_sem);
+
+	prev_refcount = dss_inner_clk_refcount++;
+	if (!prev_refcount && !fastboot_enable) {
+		outp32(dss_base + DSS_CMDLIST_OFFSET + CMD_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG0_SCL_OFFSET + SCF_COEF_MEM_CTRL,
+		       0x00000088);
+		outp32(dss_base + DSS_RCH_VG0_SCL_OFFSET + SCF_LB_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG0_ARSR_OFFSET + ARSR2P_LB_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG0_DMA_OFFSET + VPP_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG0_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG0_DMA_OFFSET + AFBCD_MEM_CTRL,
+		       0x00008888);
+
+		outp32(dss_base + DSS_RCH_VG1_SCL_OFFSET + SCF_COEF_MEM_CTRL,
+		       0x00000088);
+		outp32(dss_base + DSS_RCH_VG1_SCL_OFFSET + SCF_LB_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG1_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG1_DMA_OFFSET + AFBCD_MEM_CTRL,
+		       0x00008888);
+
+		outp32(dss_base + DSS_RCH_VG2_SCL_OFFSET + SCF_COEF_MEM_CTRL,
+		       0x00000088);
+		outp32(dss_base + DSS_RCH_VG2_SCL_OFFSET + SCF_LB_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_VG2_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+
+		outp32(dss_base + DSS_RCH_G0_SCL_OFFSET + SCF_COEF_MEM_CTRL,
+		       0x00000088);
+		outp32(dss_base + DSS_RCH_G0_SCL_OFFSET + SCF_LB_MEM_CTRL,
+		       0x0000008);
+		outp32(dss_base + DSS_RCH_G0_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_G0_DMA_OFFSET + AFBCD_MEM_CTRL,
+		       0x00008888);
+
+		outp32(dss_base + DSS_RCH_G1_SCL_OFFSET + SCF_COEF_MEM_CTRL,
+		       0x00000088);
+		outp32(dss_base + DSS_RCH_G1_SCL_OFFSET + SCF_LB_MEM_CTRL,
+		       0x0000008);
+		outp32(dss_base + DSS_RCH_G1_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_G1_DMA_OFFSET + AFBCD_MEM_CTRL,
+		       0x00008888);
+
+		outp32(dss_base + DSS_RCH_D0_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_D0_DMA_OFFSET + AFBCD_MEM_CTRL,
+		       0x00008888);
+		outp32(dss_base + DSS_RCH_D1_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_D2_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_RCH_D3_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+
+		outp32(dss_base + DSS_WCH0_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_WCH0_DMA_OFFSET + AFBCE_MEM_CTRL,
+		       0x00000888);
+		outp32(dss_base + DSS_WCH0_DMA_OFFSET + ROT_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_WCH1_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_WCH1_DMA_OFFSET + AFBCE_MEM_CTRL,
+		       0x00000888);
+		outp32(dss_base + DSS_WCH1_DMA_OFFSET + ROT_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_WCH2_DMA_OFFSET + DMA_BUF_MEM_CTRL,
+		       0x00000008);
+		outp32(dss_base + DSS_WCH2_DMA_OFFSET + ROT_MEM_CTRL,
+		       0x00000008);
+	}
+
+	HISI_FB_DEBUG("fb%d, dss_inner_clk_refcount=%d\n",
+		      hisifd->index, dss_inner_clk_refcount);
+
+	up(&hisi_fb_dss_inner_clk_sem);
+}
+
+void dss_inner_clk_common_disable(struct hisi_fb_data_type *hisifd)
+{
+	int new_refcount = 0;
+
+	BUG_ON(hisifd == NULL);
+
+	down(&hisi_fb_dss_inner_clk_sem);
+	new_refcount = --dss_inner_clk_refcount;
+	WARN_ON(new_refcount < 0);
+	if (!new_refcount) {
+		;
+	}
+
+	HISI_FB_DEBUG("fb%d, dss_inner_clk_refcount=%d\n",
+		      hisifd->index, dss_inner_clk_refcount);
+	up(&hisi_fb_dss_inner_clk_sem);
+}
+
+void dss_inner_clk_pdp_enable(struct hisi_fb_data_type *hisifd,
+			      bool fastboot_enable)
+{
+	char __iomem *dss_base = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	dss_base = hisifd->dss_base;
+
+	if (fastboot_enable) return;
+
+	outp32(dss_base + DSS_IFBC_OFFSET + IFBC_MEM_CTRL, 0x00000088);
+	outp32(dss_base + DSS_DSC_OFFSET + DSC_MEM_CTRL, 0x00000888);
+	outp32(dss_base + DSS_LDI0_OFFSET + LDI_MEM_CTRL, 0x00000008);
+	outp32(dss_base + DSS_DBUF0_OFFSET + DBUF_MEM_CTRL, 0x00000008);
+	outp32(dss_base + DSS_DPP_DITHER_OFFSET + DITHER_MEM_CTRL, 0x00000008);
+}
+
+void dss_inner_clk_pdp_disable(struct hisi_fb_data_type *hisifd)
+{
+}
+
+void dss_inner_clk_sdp_enable(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dss_base = NULL;
+
+	BUG_ON(hisifd == NULL);
+	dss_base = hisifd->dss_base;
+
+	outp32(dss_base + DSS_LDI1_OFFSET + LDI_MEM_CTRL, 0x00000008);
+	outp32(dss_base + DSS_DBUF1_OFFSET + DBUF_MEM_CTRL, 0x00000008);
+}
+
+void dss_inner_clk_sdp_disable(struct hisi_fb_data_type *hisifd)
+{
+}
+
+void init_dpp(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dpp_base = NULL;
+	struct hisi_panel_info *pinfo = NULL;
+
+	BUG_ON(hisifd == NULL);
+	pinfo = &(hisifd->panel_info);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		dpp_base = hisifd->dss_base + DSS_DPP_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	outp32(dpp_base + DPP_IMG_SIZE_BEF_SR,
+	       (DSS_HEIGHT(pinfo->yres) << 16) | DSS_WIDTH(pinfo->xres));
+	outp32(dpp_base + DPP_IMG_SIZE_AFT_SR,
+	       (DSS_HEIGHT(pinfo->yres) << 16) | DSS_WIDTH(pinfo->xres));
+
+#ifdef CONFIG_HISI_FB_COLORBAR_USED
+	outp32(dpp_base + DPP_CLRBAR_CTRL, (0x30 << 24) | (0 << 1) | 0x1);
+	set_reg(dpp_base + DPP_CLRBAR_1ST_CLR, 0xFF, 8, 16);
+	set_reg(dpp_base + DPP_CLRBAR_2ND_CLR, 0xFF, 8, 8);
+	set_reg(dpp_base + DPP_CLRBAR_3RD_CLR, 0xFF, 8, 0);
+#endif
+}
+
+static void init_dsc(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dsc_base = NULL;
+	struct hisi_panel_info *pinfo = NULL;
+	struct dsc_panel_info *dsc = NULL;
+
+	uint32_t dsc_en = 0;
+	uint32_t pic_width = 0;
+	uint32_t pic_height = 0;
+	uint32_t chunk_size = 0;
+	uint32_t groups_per_line = 0;
+	uint32_t rbs_min = 0;
+	uint32_t hrd_delay = 0;
+	uint32_t target_bpp_x16 = 0;
+	uint32_t num_extra_mux_bits = 0;
+	uint32_t slice_bits = 0;
+	uint32_t final_offset = 0;
+	uint32_t final_scale = 0;
+	uint32_t nfl_bpg_offset = 0;
+	uint32_t groups_total = 0;
+	uint32_t slice_bpg_offset = 0;
+	uint32_t scale_increment_interval = 0;
+	uint32_t initial_scale_value = 0;
+	uint32_t scale_decrement_interval = 0;
+	uint32_t adjustment_bits = 0;
+	uint32_t adj_bits_per_grp = 0;
+	uint32_t bits_per_grp = 0;
+	uint32_t slices_per_line = 0;
+	uint32_t pic_line_grp_num = 0;
+
+	BUG_ON(hisifd == NULL);
+	pinfo = &(hisifd->panel_info);
+	dsc = &(pinfo->vesa_dsc);
+
+	dsc_base = hisifd->dss_base + DSS_DSC_OFFSET;
+
+	if ((pinfo->ifbc_type == IFBC_TYPE_VESA2X_SINGLE) ||
+	    (pinfo->ifbc_type == IFBC_TYPE_VESA3X_SINGLE)) {
+
+		dsc_en = 0x5;
+		pic_width = DSS_WIDTH(pinfo->xres);
+		outp32(hisifd->dss_base + DSS_LDI0_OFFSET + LDI_VESA_CLK_SEL,
+		       0);
+	} else {
+
+		dsc_en = 0xb;
+		pic_width = DSS_WIDTH(pinfo->xres / 2);
+		outp32(hisifd->dss_base + DSS_LDI0_OFFSET + LDI_VESA_CLK_SEL,
+		       1);
+	}
+
+	pic_height = DSS_HEIGHT(pinfo->yres);
+	chunk_size = ROUND1((dsc->slice_width + 1) * dsc->bits_per_pixel, 8);
+
+	groups_per_line = (dsc->slice_width + 3) / 3;
+	rbs_min =
+	    dsc->rc_model_size - dsc->initial_offset +
+	    dsc->initial_xmit_delay * dsc->bits_per_pixel +
+	    groups_per_line * dsc->first_line_bpg_offset;
+	hrd_delay = ROUND1(rbs_min, dsc->bits_per_pixel);
+
+	target_bpp_x16 = dsc->bits_per_pixel * 16;
+	slice_bits = 8 * chunk_size * (dsc->slice_height + 1);
+
+	num_extra_mux_bits =
+	    3 * (dsc->mux_word_size + (4 * dsc->bits_per_component + 4) - 2);
+	while ((num_extra_mux_bits > 0)
+	       && ((slice_bits - num_extra_mux_bits) % dsc->mux_word_size))
+		num_extra_mux_bits--;
+
+	final_offset = dsc->rc_model_size -
+		((dsc->initial_xmit_delay * target_bpp_x16 + 8) >> 4) +
+		num_extra_mux_bits;
+
+	final_scale =
+	    8 * dsc->rc_model_size / (dsc->rc_model_size - final_offset);
+
+	nfl_bpg_offset =
+		ROUND1(dsc->first_line_bpg_offset << OFFSET_FRACTIONAL_BITS, dsc->slice_height);
+
+	groups_total = groups_per_line * (dsc->slice_height + 1);
+	slice_bpg_offset =
+		ROUND1((1 << OFFSET_FRACTIONAL_BITS) *
+			(dsc->rc_model_size - dsc->initial_offset + num_extra_mux_bits),
+			groups_total);
+
+	scale_increment_interval =
+		(1 << OFFSET_FRACTIONAL_BITS) * final_offset /
+		 ((final_scale - 9) * (nfl_bpg_offset + slice_bpg_offset));
+
+	initial_scale_value =
+	    8 * dsc->rc_model_size / (dsc->rc_model_size - dsc->initial_offset);
+	if (groups_per_line < initial_scale_value - 8) {
+		initial_scale_value = groups_per_line + 8;
+	}
+
+	if (initial_scale_value > 8) {
+		scale_decrement_interval =
+		    groups_per_line / (initial_scale_value - 8);
+	} else {
+		scale_decrement_interval = 4095;
+	}
+
+	adjustment_bits =
+	    (8 - (dsc->bits_per_pixel * (dsc->slice_width + 1)) % 8) % 8;
+
+	adj_bits_per_grp = dsc->bits_per_pixel * 3 - 3;
+	bits_per_grp = dsc->bits_per_pixel * 3;
+	slices_per_line = (pic_width > dsc->slice_width) ? 1 : 0;
+
+	pic_line_grp_num =
+	    ((dsc->slice_width + 3) / 3) * (slices_per_line + 1) - 1;
+
+	set_reg(dsc_base + DSC_REG_DEFAULT, 0x1, 1, 0);
+	set_reg(dsc_base + DSC_EN, dsc_en, 4, 0);
+	set_reg(dsc_base + DSC_CTRL,
+		dsc->bits_per_component | (dsc->linebuf_depth << 4) |
+		(dsc->block_pred_enable << 10) |
+		(0x1 << 11) | (dsc->bits_per_pixel << 16), 26, 0);
+
+	set_reg(dsc_base + DSC_PIC_SIZE, (pic_width << 16) | pic_height, 32, 0);
+
+	set_reg(dsc_base + DSC_SLICE_SIZE,
+		(dsc->slice_width << 16) | dsc->slice_height, 32, 0);
+
+	set_reg(dsc_base + DSC_CHUNK_SIZE, chunk_size, 16, 0);
+
+	set_reg(dsc_base + DSC_INITIAL_DELAY, dsc->initial_xmit_delay |
+		((hrd_delay - dsc->initial_xmit_delay) << 16), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_PARAM0,
+		initial_scale_value | (scale_increment_interval << 16), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_PARAM1,
+		(dsc->first_line_bpg_offset << 16) | scale_decrement_interval,
+		21, 0);
+
+	set_reg(dsc_base + DSC_RC_PARAM2,
+		nfl_bpg_offset | (slice_bpg_offset << 16), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_PARAM3,
+		((final_offset << 16) | dsc->initial_offset), 32, 0);
+
+	set_reg(dsc_base + DSC_FLATNESS_QP_TH,
+		((dsc->flatness_max_qp << 16) | (dsc->flatness_min_qp << 0)),
+		24, 0);
+
+	set_reg(dsc_base + DSC_RC_PARAM4,
+		((dsc->rc_edge_factor << 20) | (dsc->rc_model_size << 0)), 24,
+		0);
+
+	set_reg(dsc_base + DSC_RC_PARAM5,
+		((dsc->rc_tgt_offset_lo << 20) | (dsc->rc_tgt_offset_hi << 16) |
+		 (dsc->rc_quant_incr_limit1 << 8) |
+		 (dsc->rc_quant_incr_limit0 << 0)), 24, 0);
+
+	set_reg(dsc_base + DSC_RC_BUF_THRESH0,
+		((dsc->rc_buf_thresh0 << 24) | (dsc->rc_buf_thresh1 << 16) |
+		 (dsc->rc_buf_thresh2 << 8) | (dsc->rc_buf_thresh3 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_BUF_THRESH1,
+		((dsc->rc_buf_thresh4 << 24) | (dsc->rc_buf_thresh5 << 16) |
+		 (dsc->rc_buf_thresh6 << 8) |
+		 (dsc->rc_buf_thresh7 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_BUF_THRESH2,
+		((dsc->rc_buf_thresh8 << 24) | (dsc->rc_buf_thresh9 << 16) |
+		 (dsc->rc_buf_thresh10 << 8) |
+		 (dsc->rc_buf_thresh11 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_BUF_THRESH3,
+		((dsc->rc_buf_thresh12 << 24) |
+		 (dsc->rc_buf_thresh13 << 16)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM0,
+		((dsc->range_min_qp0 << 27) | (dsc->range_max_qp0 << 22) |
+		 (dsc->range_bpg_offset0 << 16) | (dsc->range_min_qp1 << 11) |
+		 (dsc->range_max_qp1 << 6) | (dsc->range_bpg_offset1 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM1,
+		((dsc->range_min_qp2 << 27) | (dsc->range_max_qp2 << 22) |
+		 (dsc->range_bpg_offset2 << 16) |
+		 (dsc->range_min_qp3 << 11) | (dsc->range_max_qp3 << 6) |
+		 (dsc->range_bpg_offset3 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM2,
+		((dsc->range_min_qp4 << 27) | (dsc->range_max_qp4 << 22) |
+		 (dsc->range_bpg_offset4 << 16) |
+		 (dsc->range_min_qp5 << 11) | (dsc->range_max_qp5 << 6) |
+		 (dsc->range_bpg_offset5 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM3,
+		((dsc->range_min_qp6 << 27) | (dsc->range_max_qp6 << 22) |
+		 (dsc->range_bpg_offset6 << 16) |
+		 (dsc->range_min_qp7 << 11) | (dsc->range_max_qp7 << 6) |
+		 (dsc->range_bpg_offset7 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM4,
+		((dsc->range_min_qp8 << 27) | (dsc->range_max_qp8 << 22) |
+		 (dsc->range_bpg_offset8 << 16) |
+		 (dsc->range_min_qp9 << 11) | (dsc->range_max_qp9 << 6) |
+		 (dsc->range_bpg_offset9 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM5,
+		((dsc->range_min_qp10 << 27) | (dsc->range_max_qp10 << 22) |
+		 (dsc->range_bpg_offset10 << 16) |
+		 (dsc->range_min_qp11 << 11) | (dsc->range_max_qp11 << 6) |
+		 (dsc->range_bpg_offset11 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM6,
+		((dsc->range_min_qp12 << 27) | (dsc->range_max_qp12 << 22) |
+		 (dsc->range_bpg_offset12 << 16) |
+		 (dsc->range_min_qp13 << 11) | (dsc->range_max_qp13 << 6) |
+		 (dsc->range_bpg_offset13 << 0)), 32, 0);
+
+	set_reg(dsc_base + DSC_RC_RANGE_PARAM7,
+		((dsc->range_min_qp14 << 27) | (dsc->range_max_qp14 << 22) |
+		 (dsc->range_bpg_offset14 << 16)), 32, 0);
+
+	set_reg(dsc_base + DSC_ADJUSTMENT_BITS, adjustment_bits, 4, 0);
+
+	set_reg(dsc_base + DSC_BITS_PER_GRP,
+		bits_per_grp | (adj_bits_per_grp << 8), 14, 0);
+
+	set_reg(dsc_base + DSC_MULTI_SLICE_CTL, slices_per_line |
+		(pic_line_grp_num << 16), 32, 0);
+
+	if ((chunk_size % 3 == 0)) {
+		set_reg(dsc_base + DSC_OUT_CTRL, 0x0, 1, 0);
+
+	} else if ((chunk_size % 2 == 0)) {
+		set_reg(dsc_base + DSC_OUT_CTRL, 0x1, 1, 0);
+
+	} else {
+		HISI_FB_ERR
+		    ("fb%d, chunk_size should be mode by 3 or 2,"
+		     " but chunk_size = %u\n",
+		     hisifd->index, chunk_size);
+		return;
+	}
+
+	set_reg(dsc_base + DSC_CLK_SEL, 0x0, 32, 0);
+	set_reg(dsc_base + DSC_CLK_EN, 0x7, 32, 0);
+	set_reg(dsc_base + DSC_MEM_CTRL, 0x0, 32, 0);
+	set_reg(dsc_base + DSC_ST_DATAIN, 0x0, 28, 0);
+	set_reg(dsc_base + DSC_ST_DATAOUT, 0x0, 16, 0);
+	set_reg(dsc_base + DSC0_ST_SLC_POS, 0x0, 28, 0);
+	set_reg(dsc_base + DSC1_ST_SLC_POS, 0x0, 28, 0);
+	set_reg(dsc_base + DSC0_ST_PIC_POS, 0x0, 28, 0);
+	set_reg(dsc_base + DSC1_ST_PIC_POS, 0x0, 28, 0);
+	set_reg(dsc_base + DSC0_ST_FIFO, 0x0, 14, 0);
+	set_reg(dsc_base + DSC1_ST_FIFO, 0x0, 14, 0);
+	set_reg(dsc_base + DSC0_ST_LINEBUF, 0x0, 24, 0);
+	set_reg(dsc_base + DSC1_ST_LINEBUF, 0x0, 24, 0);
+	set_reg(dsc_base + DSC_ST_ITFC, 0x0, 10, 0);
+	set_reg(dsc_base + DSC_RD_SHADOW_SEL, 0x1, 1, 0);
+	set_reg(dsc_base + DSC_REG_DEFAULT, 0x0, 1, 0);
+}
+
+void init_ifbc(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *ifbc_base = NULL;
+	struct hisi_panel_info *pinfo = NULL;
+	uint32_t mipi_idx = 0;
+	uint32_t comp_mode = 0;
+
+	uint32_t ifbc_out_mode = 0;
+	uint32_t dpk_mode_sel = 0;
+	uint32_t dup_mode_sel = 0;
+	uint32_t porch_num = 0;
+	uint32_t insert_byte_num = 0;
+	uint32_t insert_byte = 0;
+	uint32_t num_pad = 0;
+
+	BUG_ON(hisifd == NULL);
+	pinfo = &(hisifd->panel_info);
+	BUG_ON((pinfo->ifbc_type < IFBC_TYPE_NONE)
+	       || (pinfo->ifbc_type >= IFBC_TYPE_MAX));
+
+	/* VESA_CLK_SEL is set to 0 for initial, 1 is needed only by vesa dual pipe compress */
+	set_reg(hisifd->dss_base + DSS_LDI0_OFFSET + LDI_VESA_CLK_SEL, 0, 1, 0);
+
+	if (pinfo->ifbc_type == IFBC_TYPE_NONE)
+		return;
+
+	if (!HISI_DSS_SUPPORT_DPP_MODULE_BIT(DPP_MODULE_IFBC))
+		return;
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ifbc_base = hisifd->dss_base + DSS_IFBC_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	mipi_idx = is_dual_mipi_panel(hisifd) ? 1 : 0;
+	comp_mode = g_mipi_ifbc_division[mipi_idx][pinfo->ifbc_type].comp_mode;
+
+	if (is_ifbc_vesa_panel(hisifd)) {
+		init_dsc(hisifd);
+		set_reg(ifbc_base + IFBC_CTRL, comp_mode, 3, 0);
+		return;
+	}
+
+	if (pinfo->bpp == LCD_RGB888)
+		ifbc_out_mode = 1;
+	else if (pinfo->bpp == LCD_RGB565)
+		ifbc_out_mode = 0;
+
+	if (((pinfo->ifbc_type == IFBC_TYPE_ORISE2X)
+	     && (pinfo->ifbc_cmp_dat_rev0 == 1))
+	    || ((pinfo->ifbc_type == IFBC_TYPE_RSP3X)
+		 && (pinfo->type != PANEL_MIPI_VIDEO) && (pinfo->xres % 3 != 0)))
+		if (pinfo->ifbc_auto_sel != 0) {
+			HISI_FB_ERR("fb%d, auto_sel = %u not support!",
+				    hisifd->index, pinfo->ifbc_auto_sel);
+			return;
+		}
+
+	if (pinfo->ifbc_type == IFBC_TYPE_ORISE2X) {
+		if ((pinfo->xres % 2 != 0) && (pinfo->yres % 2 != 0)) {
+			HISI_FB_ERR
+			    ("fb%d, IFBC_ORISE2X not support (xres = %u, yres = %u)!",
+			     hisifd->index, pinfo->xres, pinfo->yres);
+			return;
+		}
+
+		dpk_mode_sel = 1;
+		dup_mode_sel = 2;
+		porch_num = 0;
+	} else if (pinfo->ifbc_type == IFBC_TYPE_ORISE3X) {
+		dpk_mode_sel = 0;
+		dup_mode_sel = 3;
+		porch_num = 5;
+	} else if (pinfo->ifbc_type == IFBC_TYPE_HIMAX2X) {
+		if ((pinfo->xres % 2 != 0) && (pinfo->yres % 2 != 0)) {
+			HISI_FB_ERR
+			    ("fb%d, IFBC_HIMAX2X not support (xres = %u, yres = %u)!",
+			     hisifd->index, pinfo->xres, pinfo->yres);
+			return;
+		}
+
+		dpk_mode_sel = 1;
+		dup_mode_sel = 2;
+		porch_num = 0;
+	} else if (pinfo->ifbc_type == IFBC_TYPE_RSP2X) {
+		dpk_mode_sel = 1;
+		dup_mode_sel = 0;
+		porch_num = 0;
+
+		if ((pinfo->type == PANEL_MIPI_CMD) ||
+		    (pinfo->type == PANEL_DUAL_MIPI_CMD)) {
+			num_pad = (4 - pinfo->xres % 4) % 4;
+		} else {
+			num_pad = 0;
+		}
+	} else if (pinfo->ifbc_type == IFBC_TYPE_RSP3X) {
+		if ((pinfo->yres % 2 != 0) || (pinfo->yres < 8)) {
+			HISI_FB_ERR
+			    ("fb%d, IFBC_RSP3X not support (xres = %u, yres = %u)!",
+			     hisifd->index, pinfo->xres, pinfo->yres);
+			return;
+		}
+
+		dpk_mode_sel = 2;
+		dup_mode_sel = 1;
+		porch_num = 0;
+
+		insert_byte = DSS_WIDTH(pinfo->xres) / (mipi_idx + 1) + 1;
+
+		if ((pinfo->type == PANEL_MIPI_VIDEO) ||
+		    (pinfo->type == PANEL_DUAL_MIPI_VIDEO)) {
+			insert_byte_num = (3 - insert_byte % 3) % 3;
+			num_pad = (8 - pinfo->xres % 8) % 8;
+		} else if ((pinfo->type == PANEL_MIPI_CMD) ||
+			   (pinfo->type == PANEL_DUAL_MIPI_CMD)) {
+			insert_byte_num = 0;
+			num_pad = (4 - pinfo->xres % 4) % 4;
+		}
+	}
+	set_reg(ifbc_base + IFBC_SIZE,
+		((DSS_WIDTH(pinfo->xres) << 16) | DSS_HEIGHT(pinfo->yres)), 32, 0);
+
+	set_reg(ifbc_base + IFBC_CTRL, comp_mode, 3, 0);
+	set_reg(ifbc_base + IFBC_CTRL, ifbc_out_mode, 1, 3);
+	set_reg(ifbc_base + IFBC_CTRL, pinfo->ifbc_cmp_dat_rev0, 1, 4);
+	set_reg(ifbc_base + IFBC_CTRL, pinfo->ifbc_cmp_dat_rev1, 1, 5);
+	set_reg(ifbc_base + IFBC_CTRL, pinfo->ifbc_auto_sel, 1, 6);
+
+	if (pinfo->ifbc_auto_sel == 0) {
+		set_reg(ifbc_base + IFBC_CTRL, dpk_mode_sel, 3, 7);
+		set_reg(ifbc_base + IFBC_CTRL, dup_mode_sel, 3, 10);
+		set_reg(ifbc_base + IFBC_CTRL, porch_num, 8, 13);
+		set_reg(ifbc_base + IFBC_INSERT,
+			insert_byte_num | (insert_byte << 16), 32, 0);
+
+		set_reg(ifbc_base + IFBC_PAD, num_pad, 3, 0);
+	}
+
+	if (pinfo->ifbc_type == IFBC_TYPE_ORISE3X) {
+		if (pinfo->ifbc_orise_ctr == 1) {
+			set_reg(ifbc_base + IFBC_CORE_GT, 0x0, 2, 0);
+
+			if (pinfo->ifbc_orise_ctl == IFBC_ORISE_CTL_8LINE) {
+				set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0208, 32, 0);
+
+			} else if (pinfo->ifbc_orise_ctl == IFBC_ORISE_CTL_16LINE) {
+				set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0210, 32, 0);
+			} else if (pinfo->ifbc_orise_ctl == IFBC_ORISE_CTL_32LINE) {
+				set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0220, 32, 0);
+			} else {
+				set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0200, 32, 0);
+			}
+
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0300, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0419, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0500, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x063f, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0700, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0801, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0900, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0a64, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0b00, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0c5c, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0d00, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0e01, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x0f00, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x10a0, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x1100, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x125f, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x1300, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x14a0, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x1500, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x16ff, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x1700, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x200c, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x2100, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x4000, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x4100, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x4200, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x4300, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x4800, 32, 0);
+			set_reg(ifbc_base + IFBC_ORISE_CTL, 0x4900, 32, 0);
+		} else {
+			set_reg(ifbc_base + IFBC_CORE_GT, 0x2, 2, 0);
+		}
+	}
+
+	set_reg(ifbc_base + IFBC_CLK_SEL, 0x0, 32, 0);
+	set_reg(ifbc_base + IFBC_EN, 0x3, 2, 0);
+}
+
+void init_post_scf(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dpp_base = NULL;
+	char __iomem *scf_lut_base = NULL;
+
+	struct hisi_panel_info *pinfo = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	pinfo = &(hisifd->panel_info);
+
+	dpp_base = hisifd->dss_base + DSS_DPP_OFFSET;
+	scf_lut_base = hisifd->dss_base + DSS_POST_SCF_LUT_OFFSET;
+
+	if (!HISI_DSS_SUPPORT_DPP_MODULE_BIT(DPP_MODULE_POST_SCF)) {
+		return;
+	}
+
+	/* ARSR1P memory shutdown
+	   outp32(dpp_base + DPP_ARSR1P_MEM_CTRL, 0X4); */
+
+	pinfo->post_scf_support = 1;
+	hisi_dss_post_scl_load_filter_coef(hisifd, false, scf_lut_base,
+					   SCL_COEF_RGB_IDX);
+
+	return;
+}
+
+void init_dbuf(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dbuf_base = NULL;
+	struct hisi_panel_info *pinfo = NULL;
+	int sram_valid_num = 0;
+	int sram_max_mem_depth = 0;
+	int sram_min_support_depth = 0;
+
+	uint32_t thd_rqos_in = 0;
+	uint32_t thd_rqos_out = 0;
+	uint32_t thd_wqos_in = 0;
+	uint32_t thd_wqos_out = 0;
+	uint32_t thd_cg_in = 0;
+	uint32_t thd_cg_out = 0;
+	uint32_t thd_wr_wait = 0;
+	uint32_t thd_cg_hold = 0;
+	uint32_t thd_flux_req_befdfs_in = 0;
+	uint32_t thd_flux_req_befdfs_out = 0;
+	uint32_t thd_flux_req_aftdfs_in = 0;
+	uint32_t thd_flux_req_aftdfs_out = 0;
+	uint32_t thd_dfs_ok = 0;
+	uint32_t dfs_ok_mask = 0;
+	uint32_t thd_flux_req_sw_en = 1;
+
+	int dfs_time = 0;
+	int dfs_time_min = 0;
+	int depth = 0;
+
+	BUG_ON(hisifd == NULL);
+	pinfo = &(hisifd->panel_info);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		dbuf_base = hisifd->dss_base + DSS_DBUF0_OFFSET;
+		if (!HISI_DSS_SUPPORT_DPP_MODULE_BIT(DPP_MODULE_DBUF)) {
+			return;
+		}
+
+		if (pinfo->xres * pinfo->yres >= RES_4K_PHONE) {
+			dfs_time_min = DFS_TIME_MIN_4K;
+		} else {
+			dfs_time_min = DFS_TIME_MIN;
+		}
+
+		dfs_time = DFS_TIME;
+		depth = DBUF0_DEPTH;
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		dbuf_base = hisifd->dss_base + DSS_DBUF1_OFFSET;
+
+		dfs_time = DFS_TIME;
+		dfs_time_min = DFS_TIME_MIN;
+		depth = DBUF1_DEPTH;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	/*
+	 ** int K = 0;
+	 ** int Tp = 1000000  / pinfo->pxl_clk_rate;
+	 ** K = (pinfo->ldi.h_pulse_width + pinfo->ldi.h_back_porch + pinfo->xres +
+	 **     pinfo->ldi.h_front_porch) / pinfo->xres;
+	 ** thd_cg_out = dfs_time / (Tp * K * 6);
+	 */
+	if (pinfo->pxl_clk_rate_div <= 0)
+		pinfo->pxl_clk_rate_div = 1;
+
+	thd_cg_out = (dfs_time * pinfo->pxl_clk_rate * pinfo->xres) /
+	    (((pinfo->ldi.h_pulse_width + pinfo->ldi.h_back_porch +
+	       pinfo->ldi.h_front_porch) * pinfo->pxl_clk_rate_div +
+	      pinfo->xres) * 6 * 1000000UL);
+	sram_valid_num = thd_cg_out / depth;
+	thd_cg_in = (sram_valid_num + 1) * depth - 1;
+
+	sram_max_mem_depth = (sram_valid_num + 1) * depth;
+
+	thd_rqos_in = thd_cg_out * 85 / 100;
+	thd_rqos_out = thd_cg_out;
+	thd_flux_req_befdfs_in = GET_FLUX_REQ_IN(sram_max_mem_depth);
+	thd_flux_req_befdfs_out = GET_FLUX_REQ_OUT(sram_max_mem_depth);
+
+	sram_min_support_depth =
+	    dfs_time_min * pinfo->xres / (1000000 / 60 /
+					  (pinfo->yres +
+					   pinfo->ldi.v_back_porch +
+					   pinfo->ldi.v_front_porch +
+					   pinfo->ldi.v_pulse_width) *
+					  (DBUF_WIDTH_BIT / 3 / BITS_PER_BYTE));
+
+	/* thd_flux_req_aftdfs_in   =[(sram_valid_num+1)*depth - 50*HSIZE/((1000000/60/(VSIZE+VFP+VBP+VSW))*6)]/3 */
+	thd_flux_req_aftdfs_in =
+	    (sram_max_mem_depth - sram_min_support_depth) / 3;
+	/* thd_flux_req_aftdfs_out  =  2*[(sram_valid_num+1)* depth - 50*HSIZE/((1000000/60/(VSIZE+VFP+VBP+VSW))*6)]/3 */
+	thd_flux_req_aftdfs_out =
+	    2 * (sram_max_mem_depth - sram_min_support_depth) / 3;
+
+	thd_dfs_ok = thd_flux_req_befdfs_in;
+
+	HISI_FB_DEBUG("sram_valid_num=%d,\n"
+		      "thd_rqos_in=0x%x\n"
+		      "thd_rqos_out=0x%x\n"
+		      "thd_cg_in=0x%x\n"
+		      "thd_cg_out=0x%x\n"
+		      "thd_flux_req_befdfs_in=0x%x\n"
+		      "thd_flux_req_befdfs_out=0x%x\n"
+		      "thd_flux_req_aftdfs_in=0x%x\n"
+		      "thd_flux_req_aftdfs_out=0x%x\n"
+		      "thd_dfs_ok=0x%x\n",
+		      sram_valid_num,
+		      thd_rqos_in,
+		      thd_rqos_out,
+		      thd_cg_in,
+		      thd_cg_out,
+		      thd_flux_req_befdfs_in,
+		      thd_flux_req_befdfs_out,
+		      thd_flux_req_aftdfs_in,
+		      thd_flux_req_aftdfs_out, thd_dfs_ok);
+
+	outp32(dbuf_base + DBUF_FRM_SIZE, pinfo->xres * pinfo->yres);
+	outp32(dbuf_base + DBUF_FRM_HSIZE, DSS_WIDTH(pinfo->xres));
+	outp32(dbuf_base + DBUF_SRAM_VALID_NUM, sram_valid_num);
+
+	outp32(dbuf_base + DBUF_THD_RQOS, (thd_rqos_out << 16) | thd_rqos_in);
+	outp32(dbuf_base + DBUF_THD_WQOS, (thd_wqos_out << 16) | thd_wqos_in);
+	outp32(dbuf_base + DBUF_THD_CG, (thd_cg_out << 16) | thd_cg_in);
+	outp32(dbuf_base + DBUF_THD_OTHER, (thd_cg_hold << 16) | thd_wr_wait);
+	outp32(dbuf_base + DBUF_THD_FLUX_REQ_BEF,
+	       (thd_flux_req_befdfs_out << 16) | thd_flux_req_befdfs_in);
+	outp32(dbuf_base + DBUF_THD_FLUX_REQ_AFT,
+	       (thd_flux_req_aftdfs_out << 16) | thd_flux_req_aftdfs_in);
+	outp32(dbuf_base + DBUF_THD_DFS_OK, thd_dfs_ok);
+	outp32(dbuf_base + DBUF_FLUX_REQ_CTRL,
+	       (dfs_ok_mask << 1) | thd_flux_req_sw_en);
+
+	outp32(dbuf_base + DBUF_DFS_LP_CTRL, 0x1);
+}
+
+static void init_ldi_pxl_div(struct hisi_fb_data_type *hisifd)
+{
+	struct hisi_panel_info *pinfo = NULL;
+	char __iomem *ldi_base = NULL;
+	uint32_t ifbc_type = 0;
+	uint32_t mipi_idx = 0;
+	uint32_t pxl0_div2_gt_en = 0;
+	uint32_t pxl0_div4_gt_en = 0;
+	uint32_t pxl0_divxcfg = 0;
+	uint32_t pxl0_dsi_gt_en = 0;
+
+	BUG_ON(hisifd == NULL);
+	pinfo = &(hisifd->panel_info);
+
+	if (hisifd->index == EXTERNAL_PANEL_IDX)
+		return;
+
+	ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+
+	ifbc_type = pinfo->ifbc_type;
+	BUG_ON((ifbc_type < IFBC_TYPE_NONE) || (ifbc_type >= IFBC_TYPE_MAX));
+
+	mipi_idx = is_dual_mipi_panel(hisifd) ? 1 : 0;
+
+	pxl0_div2_gt_en =
+	    g_mipi_ifbc_division[mipi_idx][ifbc_type].pxl0_div2_gt_en;
+	pxl0_div4_gt_en =
+	    g_mipi_ifbc_division[mipi_idx][ifbc_type].pxl0_div4_gt_en;
+	pxl0_divxcfg = g_mipi_ifbc_division[mipi_idx][ifbc_type].pxl0_divxcfg;
+	pxl0_dsi_gt_en =
+	    g_mipi_ifbc_division[mipi_idx][ifbc_type].pxl0_dsi_gt_en;
+
+	set_reg(ldi_base + LDI_PXL0_DIV2_GT_EN, pxl0_div2_gt_en, 1, 0);
+	set_reg(ldi_base + LDI_PXL0_DIV4_GT_EN, pxl0_div4_gt_en, 1, 0);
+	set_reg(ldi_base + LDI_PXL0_GT_EN, 0x1, 1, 0);
+	set_reg(ldi_base + LDI_PXL0_DSI_GT_EN, pxl0_dsi_gt_en, 2, 0);
+	set_reg(ldi_base + LDI_PXL0_DIVXCFG, pxl0_divxcfg, 3, 0);
+}
+
+void init_ldi(struct hisi_fb_data_type *hisifd, bool fastboot_enable)
+{
+	char __iomem *ldi_base = NULL;
+	struct hisi_panel_info *pinfo = NULL;
+	dss_rect_t rect = { 0, 0, 0, 0 };
+	uint32_t te0_enable = 0;
+	uint32_t te1_enable = 0;
+	uint32_t te_source = 0;
+
+	BUG_ON(hisifd == NULL);
+	pinfo = &(hisifd->panel_info);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+		te0_enable = 1;
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		te1_enable = 1;
+		ldi_base = hisifd->dss_base + DSS_LDI1_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	rect.x = 0;
+	rect.y = 0;
+	rect.w = pinfo->xres;
+	rect.h = pinfo->yres;
+	mipi_ifbc_get_rect(hisifd, &rect);
+
+	init_ldi_pxl_div(hisifd);
+
+	if (is_dual_mipi_panel(hisifd)) {
+		if (is_mipi_video_panel(hisifd)) {
+			outp32(ldi_base + LDI_DPI1_HRZ_CTRL0,
+			       (pinfo->ldi.h_back_porch +
+				DSS_WIDTH(pinfo->ldi.h_pulse_width)) << 16);
+			outp32(ldi_base + LDI_DPI1_HRZ_CTRL1, 0);
+			outp32(ldi_base + LDI_DPI1_HRZ_CTRL2,
+			       DSS_WIDTH(rect.w));
+		} else {
+			outp32(ldi_base + LDI_DPI1_HRZ_CTRL0,
+			       pinfo->ldi.h_back_porch << 16);
+			outp32(ldi_base + LDI_DPI1_HRZ_CTRL1,
+			       DSS_WIDTH(pinfo->ldi.h_pulse_width));
+			outp32(ldi_base + LDI_DPI1_HRZ_CTRL2,
+			       DSS_WIDTH(rect.w));
+		}
+
+		outp32(ldi_base + LDI_OVERLAP_SIZE,
+		       pinfo->ldi.dpi0_overlap_size |
+		       (pinfo->ldi.dpi1_overlap_size << 16));
+
+		/* dual_mode_en */
+		set_reg(ldi_base + LDI_CTRL, 1, 1, 5);
+
+		/* split mode */
+		set_reg(ldi_base + LDI_CTRL, 0, 1, 16);
+
+		/* dual lcd: 0x1, dual mipi: 0x0 */
+		set_reg(hisifd->dss_base + DSS_LDI0_OFFSET + LDI_DSI1_CLK_SEL,
+			0x0, 1, 0);
+	}
+	if (is_mipi_video_panel(hisifd)) {
+		outp32(ldi_base + LDI_DPI0_HRZ_CTRL0,
+		       pinfo->ldi.h_front_porch |
+		       ((pinfo->ldi.h_back_porch +
+				DSS_WIDTH(pinfo->ldi.h_pulse_width)) << 16));
+
+		outp32(ldi_base + LDI_DPI0_HRZ_CTRL1, 0);
+		outp32(ldi_base + LDI_DPI0_HRZ_CTRL2, DSS_WIDTH(rect.w));
+	} else {
+		outp32(ldi_base + LDI_DPI0_HRZ_CTRL0,
+		       pinfo->ldi.h_front_porch | (pinfo->ldi.h_back_porch << 16));
+		outp32(ldi_base + LDI_DPI0_HRZ_CTRL1,
+		       DSS_WIDTH(pinfo->ldi.h_pulse_width));
+		outp32(ldi_base + LDI_DPI0_HRZ_CTRL2, DSS_WIDTH(rect.w));
+	}
+	outp32(ldi_base + LDI_VRT_CTRL0,
+	       pinfo->ldi.v_front_porch | (pinfo->ldi.v_back_porch << 16));
+	outp32(ldi_base + LDI_VRT_CTRL1, DSS_HEIGHT(pinfo->ldi.v_pulse_width));
+	outp32(ldi_base + LDI_VRT_CTRL2, DSS_HEIGHT(rect.h));
+
+	outp32(ldi_base + LDI_PLR_CTRL,
+	       pinfo->ldi.vsync_plr | (pinfo->ldi.hsync_plr << 1) |
+	       (pinfo->ldi.pixelclk_plr << 2) | (pinfo->ldi.data_en_plr << 3));
+
+	set_reg(ldi_base + LDI_CTRL, pinfo->bpp, 2, 3);
+	set_reg(ldi_base + LDI_CTRL, pinfo->bgr_fmt, 1, 13);
+
+	outp32(ldi_base + LDI_VINACT_MSK_LEN, pinfo->ldi.v_front_porch);
+	outp32(ldi_base + LDI_CMD_EVENT_SEL, 0x1);
+
+	/* for 1Hz LCD and mipi command LCD */
+	if (is_mipi_cmd_panel(hisifd)) {
+		set_reg(ldi_base + LDI_DSI_CMD_MOD_CTRL, 0x1, 1, 0);
+
+		/* DSI_TE_CTRL
+		 * te_source = 0, select te_pin
+		 * te_source = 1, select te_triger
+		 */
+		te_source = 0;
+
+		set_reg(ldi_base + LDI_DSI_TE_CTRL, 0x1, 1, 0);
+		set_reg(ldi_base + LDI_DSI_TE_CTRL, 0x0, 2, 1);
+		set_reg(ldi_base + LDI_DSI_TE_CTRL, te_source, 1, 3);
+		if (te_source == 0) {
+			set_reg(ldi_base + LDI_DSI_TE_CTRL, te0_enable, 1, 6);
+			set_reg(ldi_base + LDI_DSI_TE_CTRL, te1_enable, 1, 7);
+		} else {
+			set_reg(ldi_base + LDI_DSI_TE_CTRL, te0_enable, 1, 4);
+			set_reg(ldi_base + LDI_DSI_TE_CTRL, te1_enable, 1, 5);
+		}
+		set_reg(ldi_base + LDI_DSI_TE_CTRL, 0x0, 1, 8);
+		set_reg(ldi_base + LDI_DSI_TE_CTRL, 0x0, 4, 9);
+		set_reg(ldi_base + LDI_DSI_TE_CTRL, 0x0, 4, 13);
+		set_reg(ldi_base + LDI_DSI_TE_CTRL, 0x1, 1, 17);
+
+		/* TBD:(dsi_te_hs_num+vactive)*htotal/clk_pxl0_div+0.00004<1/60+vs_te_time+(vactive*hotal) /clk_ddic_rd */
+		set_reg(ldi_base + LDI_DSI_TE_HS_NUM, 0x0, 32, 0);
+		set_reg(ldi_base + LDI_DSI_TE_HS_WD, 0x24024, 32, 0);
+
+		/* dsi_te0_vs_wd = lcd_te_width / T_pxl_clk, experience lcd_te_width = 2us */
+		if (pinfo->pxl_clk_rate_div == 0) {
+			HISI_FB_ERR("pxl_clk_rate_div is NULL, not support !\n");
+			pinfo->pxl_clk_rate_div = 1;
+		}
+		set_reg(ldi_base + LDI_DSI_TE_VS_WD,
+			(0x3FC << 12) | (2 * pinfo->pxl_clk_rate /
+					 pinfo->pxl_clk_rate_div / 1000000), 32, 0);
+	} else {
+		set_reg(ldi_base + LDI_DSI_CMD_MOD_CTRL, 0x1, 1, 1);
+	}
+
+#ifdef CONFIG_HISI_FB_COLORBAR_USED
+	set_reg(ldi_base + LDI_CTRL, DSS_WIDTH(0x3c), 7, 6);
+	set_reg(ldi_base + LDI_WORK_MODE, 0x0, 1, 1);
+	set_reg(ldi_base + LDI_WORK_MODE, 0x0, 1, 0);
+#else
+	set_reg(ldi_base + LDI_WORK_MODE, 0x1, 1, 0);
+#endif
+
+	if (is_mipi_cmd_panel(hisifd)) {
+		set_reg(ldi_base + LDI_FRM_MSK,
+			(hisifd->frame_update_flag == 1) ? 0x0 : 0x1, 1, 0);
+	}
+
+	if (!fastboot_enable)
+		set_reg(ldi_base + LDI_CTRL, 0x0, 1, 0);
+
+	HISI_FB_DEBUG("-.!\n");
+}
+
+void deinit_ldi(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *ldi_base = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI1_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	set_reg(ldi_base + LDI_CTRL, 0, 1, 0);
+}
+
+void enable_ldi(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *ldi_base = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI1_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	/* ldi enable */
+	set_reg(ldi_base + LDI_CTRL, 0x1, 1, 0);
+}
+
+void disable_ldi(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *ldi_base = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI1_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	/* ldi disable */
+	set_reg(ldi_base + LDI_CTRL, 0x0, 1, 0);
+}
+
+/* set pixel clock to the exact value which is larger than 288M */
+int dpe_recover_pxl_clock(struct hisi_fb_data_type *hisifd)
+{
+	if ((hisifd->panel_info.pxl_clk_rate > DSS_MAX_PXL0_CLK_288M)
+	    && (hisifd->index == PRIMARY_PANEL_IDX)) {
+		if (clk_set_rate(hisifd->dss_pxl0_clk,
+		     hisifd->panel_info.pxl_clk_rate) < 0) {
+			HISI_FB_ERR
+			    ("fb%d dss_pxl0_clk clk_set_rate(%llu) failed!\n",
+			     hisifd->index, hisifd->panel_info.pxl_clk_rate);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+void ldi_frame_update(struct hisi_fb_data_type *hisifd, bool update)
+{
+	char __iomem *ldi_base = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+
+		if (is_mipi_cmd_panel(hisifd)) {
+			set_reg(ldi_base + LDI_FRM_MSK, (update ? 0x0 : 0x1), 1, 0);
+			if (update)
+				set_reg(ldi_base + LDI_CTRL, 0x1, 1, 0);
+		}
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+	}
+}
+
+void single_frame_update(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *ldi_base = NULL;
+	struct hisi_panel_info *pinfo = NULL;
+
+	BUG_ON(hisifd == NULL);
+	pinfo = &(hisifd->panel_info);
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+		if (is_mipi_cmd_panel(hisifd)) {
+			set_reg(ldi_base + LDI_FRM_MSK_UP, 0x1, 1, 0);
+			set_reg(ldi_base + LDI_CTRL, 0x1, 1, 0);
+		} else {
+			set_reg(ldi_base + LDI_CTRL, 0x1, 1, 0);
+		}
+
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI1_OFFSET;
+
+		if (is_mipi_cmd_panel(hisifd)) {
+			set_reg(ldi_base + LDI_FRM_MSK_UP, 0x1, 1, 0);
+			set_reg(ldi_base + LDI_CTRL, 0x1, 1, 0);
+		} else {
+			set_reg(ldi_base + LDI_CTRL, 0x1, 1, 0);
+		}
+	} else {
+		;
+	}
+}
+
+void dpe_interrupt_clear(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dss_base = 0;
+	uint32_t clear = 0;
+
+	BUG_ON(hisifd == NULL);
+
+	dss_base = hisifd->dss_base;
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		clear = ~0;
+		outp32(dss_base + GLB_CPU_PDP_INTS, clear);
+		outp32(dss_base + DSS_LDI0_OFFSET + LDI_CPU_ITF_INTS, clear);
+		outp32(dss_base + DSS_DPP_OFFSET + DPP_INTS, clear);
+
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_MCTL_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_WCH0_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_WCH1_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH0_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH1_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH2_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH3_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH4_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH5_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH6_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH7_INTS, clear);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_DSS_GLB_INTS, clear);
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		clear = ~0;
+		outp32(dss_base + GLB_CPU_SDP_INTS, clear);
+		outp32(dss_base + DSS_LDI1_OFFSET + LDI_CPU_ITF_INTS, clear);
+	} else if (hisifd->index == AUXILIARY_PANEL_IDX) {
+		clear = ~0;
+		outp32(dss_base + GLB_CPU_OFF_INTS, clear);
+	} else {
+		HISI_FB_ERR("fb%d, not support this device!\n", hisifd->index);
+	}
+
+}
+
+void dpe_interrupt_unmask(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dss_base = 0;
+	uint32_t unmask = 0;
+	struct hisi_panel_info *pinfo = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	pinfo = &(hisifd->panel_info);
+	dss_base = hisifd->dss_base;
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		unmask = ~0;
+		/* unmask &= ~(BIT_DPP_INTS | BIT_ITF0_INTS | BIT_DSS_GLB_INTS | BIT_MMU_IRPT_NS); */
+		unmask &= ~(BIT_DPP_INTS | BIT_ITF0_INTS | BIT_MMU_IRPT_NS);
+		outp32(dss_base + GLB_CPU_PDP_INT_MSK, unmask);
+
+		unmask = ~0;
+		if (is_mipi_cmd_panel(hisifd)) {
+			unmask &=
+			    ~(BIT_LCD_TE0_PIN | BIT_VACTIVE0_START |
+			      BIT_VACTIVE0_END | BIT_FRM_END);
+		} else {
+			unmask &=
+			    ~(BIT_VSYNC | BIT_VACTIVE0_START | BIT_VACTIVE0_END
+			      | BIT_FRM_END);
+		}
+		outp32(dss_base + DSS_LDI0_OFFSET + LDI_CPU_ITF_INT_MSK,
+		       unmask);
+
+		unmask = ~0;
+		/* unmask &= ~(BIT_CE_END_IND | BIT_BACKLIGHT_INTP); */
+		if ((pinfo->acm_ce_support == 1)
+		    && HISI_DSS_SUPPORT_DPP_MODULE_BIT(DPP_MODULE_ACE))
+			unmask &= ~(BIT_CE_END_IND);
+		if (pinfo->hiace_support == 1)
+			unmask &= ~(BIT_HIACE_IND);
+
+		outp32(dss_base + DSS_DPP_OFFSET + DPP_INT_MSK, unmask);
+
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		unmask = ~0;
+		/* unmask &= ~(BIT_SDP_ITF1_INTS  | BIT_SDP_DSS_GLB_INTS | BIT_SDP_MMU_IRPT_NS); */
+		unmask &= ~(BIT_SDP_ITF1_INTS | BIT_SDP_MMU_IRPT_NS);
+		outp32(dss_base + GLB_CPU_SDP_INT_MSK, unmask);
+
+		unmask = ~0;
+		unmask &= ~(BIT_VSYNC | BIT_VACTIVE0_START | BIT_VACTIVE0_END);
+		outp32(dss_base + DSS_LDI1_OFFSET + LDI_CPU_ITF_INT_MSK,
+		       unmask);
+	} else if (hisifd->index == AUXILIARY_PANEL_IDX) {
+		unmask = ~0;
+		unmask &=
+		    ~(BIT_OFF_WCH0_INTS | BIT_OFF_WCH1_INTS |
+		      BIT_OFF_WCH0_WCH1_FRM_END_INT | BIT_OFF_MMU_IRPT_NS);
+		outp32(dss_base + GLB_CPU_OFF_INT_MSK, unmask);
+
+		unmask = ~0;
+		unmask &= ~(BIT_OFF_CAM_WCH2_FRMEND_INTS);
+		outp32(dss_base + GLB_CPU_OFF_CAM_INT_MSK, unmask);
+	} else {
+		HISI_FB_ERR("fb%d, not support this device!\n", hisifd->index);
+	}
+
+}
+
+void dpe_interrupt_mask(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dss_base = 0;
+	uint32_t mask = 0;
+
+	BUG_ON(hisifd == NULL);
+
+	dss_base = hisifd->dss_base;
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		mask = ~0;
+		outp32(dss_base + GLB_CPU_PDP_INT_MSK, mask);
+		outp32(dss_base + DSS_LDI0_OFFSET + LDI_CPU_ITF_INT_MSK, mask);
+		outp32(dss_base + DSS_DPP_OFFSET + DPP_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_DSS_GLB_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_MCTL_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_WCH0_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_WCH1_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH0_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH1_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH2_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH3_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH4_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH5_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH6_INT_MSK, mask);
+		outp32(dss_base + DSS_DBG_OFFSET + DBG_RCH7_INT_MSK, mask);
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		mask = ~0;
+		outp32(dss_base + GLB_CPU_SDP_INT_MSK, mask);
+		outp32(dss_base + DSS_LDI1_OFFSET + LDI_CPU_ITF_INT_MSK, mask);
+	} else if (hisifd->index == AUXILIARY_PANEL_IDX) {
+		mask = ~0;
+		outp32(dss_base + GLB_CPU_OFF_INT_MSK, mask);
+		outp32(dss_base + GLB_CPU_OFF_CAM_INT_MSK, mask);
+	} else {
+		HISI_FB_ERR("fb%d, not support this device!\n", hisifd->index);
+	}
+
+}
+
+void ldi_data_gate(struct hisi_fb_data_type *hisifd, bool enble)
+{
+	char __iomem *ldi_base = NULL;
+
+	BUG_ON(hisifd == NULL);
+
+	if (!is_mipi_cmd_panel(hisifd)) {
+		hisifd->ldi_data_gate_en = (enble ? 1 : 0);
+		return;
+	}
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI0_OFFSET;
+	} else if (hisifd->index == EXTERNAL_PANEL_IDX) {
+		ldi_base = hisifd->dss_base + DSS_LDI1_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!", hisifd->index);
+		return;
+	}
+
+	if (g_ldi_data_gate_en == 1) {
+		hisifd->ldi_data_gate_en = (enble ? 1 : 0);
+		set_reg(ldi_base + LDI_CTRL, (enble ? 0x1 : 0x0), 1, 2);
+	} else {
+		hisifd->ldi_data_gate_en = 0;
+		set_reg(ldi_base + LDI_CTRL, 0x0, 1, 2);
+	}
+
+	HISI_FB_DEBUG("ldi_data_gate_en=%d!\n", hisifd->ldi_data_gate_en);
+}
+
+/* dpp csc config */
+#define CSC_ROW	(3)
+#define CSC_COL	(5)
+
+/*
+ ** Rec.601 for Computer
+ ** [ p00 p01 p02 cscidc2 cscodc2 ]
+ ** [ p10 p11 p12 cscidc1 cscodc1 ]
+ ** [ p20 p21 p22 cscidc0 cscodc0 ]
+ */
+static int CSC10B_YUV2RGB709_WIDE_MPREC0[CSC_ROW][CSC_COL] = {
+	{0x400, 0x000, 0x64d, 0x000, 0x000},
+	{0x400, 0x1f40, 0x1e21, 0x5fe, 0x000},
+	{0x400, 0x76c, 0x000, 0x5fe, 0x000}
+};
+
+static int CSC10B_RGB2YUV709_WIDE_MPREC2[CSC_ROW][CSC_COL] = {
+	{0x367, 0xb71, 0x128, 0x000, 0x000},
+	{0x1e2b, 0x19d5, 0x800, 0x000, 0x202},
+	{0x800, 0x18bc, 0x1f44, 0x000, 0x202},
+};
+
+static void init_csc10b(struct hisi_fb_data_type *hisifd,
+			char __iomem *dpp_csc10b_base)
+{
+	int (*csc_coe)[CSC_COL];
+
+	if (hisifd == NULL || dpp_csc10b_base == NULL) {
+		HISI_FB_ERR("hisifd or dpp_csc10b_base is NULL!\n");
+		return;
+	}
+
+	if (dpp_csc10b_base ==
+	    (hisifd->dss_base + DSS_DPP_CSC_RGB2YUV10B_OFFSET)) {
+		csc_coe = CSC10B_RGB2YUV709_WIDE_MPREC2;
+		outp32(dpp_csc10b_base + CSC10B_MPREC, 0x2);
+	} else if (dpp_csc10b_base ==
+		   (hisifd->dss_base + DSS_DPP_CSC_YUV2RGB10B_OFFSET)) {
+		csc_coe = CSC10B_YUV2RGB709_WIDE_MPREC0;
+		outp32(dpp_csc10b_base + CSC10B_MPREC, 0x0);
+	} else {
+		return;
+	}
+
+	outp32(dpp_csc10b_base + CSC10B_IDC0, csc_coe[2][3]);
+	outp32(dpp_csc10b_base + CSC10B_IDC1, csc_coe[1][3]);
+	outp32(dpp_csc10b_base + CSC10B_IDC2, csc_coe[0][3]);
+	outp32(dpp_csc10b_base + CSC10B_ODC0, csc_coe[2][4]);
+	outp32(dpp_csc10b_base + CSC10B_ODC1, csc_coe[1][4]);
+	outp32(dpp_csc10b_base + CSC10B_ODC2, csc_coe[0][4]);
+	outp32(dpp_csc10b_base + CSC10B_P00, csc_coe[0][0]);
+	outp32(dpp_csc10b_base + CSC10B_P01, csc_coe[0][1]);
+	outp32(dpp_csc10b_base + CSC10B_P02, csc_coe[0][2]);
+	outp32(dpp_csc10b_base + CSC10B_P10, csc_coe[1][0]);
+	outp32(dpp_csc10b_base + CSC10B_P11, csc_coe[1][1]);
+	outp32(dpp_csc10b_base + CSC10B_P12, csc_coe[1][2]);
+	outp32(dpp_csc10b_base + CSC10B_P20, csc_coe[2][0]);
+	outp32(dpp_csc10b_base + CSC10B_P21, csc_coe[2][1]);
+	outp32(dpp_csc10b_base + CSC10B_P22, csc_coe[2][2]);
+
+	outp32(dpp_csc10b_base + CSC10B_MODULE_EN, 0x1);
+}
+
+void init_dpp_csc(struct hisi_fb_data_type *hisifd)
+{
+	struct hisi_panel_info *pinfo = NULL;
+
+	if (hisifd == NULL) {
+		HISI_FB_ERR("init_dpp_csc hisifd is NULL!\n");
+		return;
+	}
+
+	pinfo = &(hisifd->panel_info);
+
+	if (pinfo->acm_support || pinfo->arsr1p_sharpness_support
+	    || pinfo->post_scf_support) {
+		init_csc10b(hisifd,
+			    hisifd->dss_base + DSS_DPP_CSC_RGB2YUV10B_OFFSET);
+		init_csc10b(hisifd,
+			    hisifd->dss_base + DSS_DPP_CSC_YUV2RGB10B_OFFSET);
+
+		set_reg(hisifd->dss_base + DSS_DPP_BITEXT0_OFFSET +
+			BIT_EXT0_CTL, 1, 1, 0);
+	}
+}
+
+void init_acm(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *acm_base = NULL;
+	struct hisi_panel_info *pinfo = NULL;
+
+	if (hisifd == NULL) {
+		HISI_FB_DEBUG("init_acm hisifd is NULL!\n");
+		return;
+	}
+
+	pinfo = &(hisifd->panel_info);
+	acm_base = hisifd->dss_base + DSS_DPP_ACM_OFFSET;
+
+	if (pinfo->acm_support != 1) {
+		outp32(acm_base + ACM_MEM_CTRL, 0x4);
+		HISI_FB_DEBUG("fb%d, not support acm!\n", hisifd->index);
+		return;
+	}
+	/* not support */
+	outp32(acm_base + ACM_MEM_CTRL, 0x4);
+}
+
+void init_igm_gmp_xcc_gm(struct hisi_fb_data_type *hisifd)
+{
+	char __iomem *dpp_base = NULL;
+	char __iomem *lcp_base = NULL;
+	char __iomem *gamma_base = NULL;
+
+	if (hisifd == NULL) {
+		HISI_FB_ERR("init_degmma_xcc_gmp hisifd is NULL!\n");
+		return;
+	}
+
+	if (hisifd->index == PRIMARY_PANEL_IDX) {
+		dpp_base = hisifd->dss_base + DSS_DPP_OFFSET;
+		lcp_base = hisifd->dss_base + DSS_DPP_LCP_OFFSET;
+		gamma_base = hisifd->dss_base + DSS_DPP_GAMA_OFFSET;
+	} else {
+		HISI_FB_ERR("fb%d, not support!\n", hisifd->index);
+		return;
+	}
+	outp32(lcp_base + LCP_DEGAMA_MEM_CTRL, 0x4);
+	outp32(lcp_base + LCP_GMP_MEM_CTRL, 0x4);
+	outp32(gamma_base + GAMA_MEM_CTRL, 0x4);
+}
diff --git a/drivers/video/fbdev/hisi/dss/hisi_dss.h b/drivers/video/fbdev/hisi/dss/hisi_dss.h
new file mode 100755
index 000000000000..8bcb1192c64e
--- /dev/null
+++ b/drivers/video/fbdev/hisi/dss/hisi_dss.h
@@ -0,0 +1,493 @@
+/* include/linux/hisi_dss.h
+ *
+ * Copyright (c) 2013-2014, Hisilicon Tech. Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _HISI_DSS_H_
+#define _HISI_DSS_H_
+
+#include <linux/types.h>
+#include <linux/fb.h>
+
+#define HISIFB_IOCTL_MAGIC 'M'
+
+#define FB_ACCEL_HI62xx     0x1
+#define FB_ACCEL_HI363x     0x2
+#define FB_ACCEL_HI365x     0x4
+#define FB_ACCEL_HI625x     0x8
+#define FB_ACCEL_HI366x     0x10
+#define FB_ACCEL_PLATFORM_TYPE_FPGA     0x10000000
+#define FB_ACCEL_PLATFORM_TYPE_ASIC     0x20000000
+
+#define HISIFB_LCD_DIRTY_REGION_INFO_GET _IOW(HISIFB_IOCTL_MAGIC, 801, struct lcd_dirty_region_info)
+#define HISIFB_PLATFORM_TYPE_GET _IOW(HISIFB_IOCTL_MAGIC, 802, int)
+
+#define HISIFB_VSYNC_CTRL _IOW(HISIFB_IOCTL_MAGIC, 0x02, unsigned int)
+#define HISIFB_DSS_CLK_RATE_SET _IOW(HISIFB_IOCTL_MAGIC, 0x04, struct dss_clk_rate)
+#define HISIFB_DIRTY_REGION_UPDT_SET _IOW(HISIFB_IOCTL_MAGIC, 0x06, int)
+#define HISIFB_DSS_MMBUF_ALLOC _IOW(HISIFB_IOCTL_MAGIC, 0x08, struct dss_mmbuf)
+#define HISIFB_DSS_MMBUF_FREE _IOW(HISIFB_IOCTL_MAGIC, 0x09, struct dss_mmbuf)
+#define HISIFB_DSS_VOLTAGE_GET _IOW(HISIFB_IOCTL_MAGIC, 0x10, struct dss_clk_rate)
+#define HISIFB_DSS_VOLTAGE_SET _IOW(HISIFB_IOCTL_MAGIC, 0x11, struct dss_clk_rate)
+
+#define HISIFB_OV_ONLINE_PLAY _IOW(HISIFB_IOCTL_MAGIC, 0x21, struct dss_overlay)
+
+#define HISIFB_IDLE_IS_ALLOWED  _IOW(HISIFB_IOCTL_MAGIC, 0x42, int)
+
+#ifndef BIT
+#define BIT(x)  (1<<(x))
+#endif
+
+/* for fb0 fb1 fb2 and so on */
+#define PRIMARY_PANEL_IDX	(0)
+#define EXTERNAL_PANEL_IDX	(1)
+#define AUXILIARY_PANEL_IDX	(2)
+
+/* lcd fps scence */
+#define LCD_FPS_SCENCE_NORMAL   (0)
+#define LCD_FPS_SCENCE_IDLE     BIT(0)
+#define LCD_FPS_SCENCE_VIDEO    BIT(1)
+#define LCD_FPS_SCENCE_GAME     BIT(2)
+#define LCD_FPS_SCENCE_WEB      BIT(3)
+#define LCD_FPS_SCENCE_EBOOK    BIT(4)
+
+#define DSS_WCH_MAX  (2)
+
+/* for YUV */
+#define MAX_PLANES	(3)
+
+enum dss_wb_compose_type {
+	DSS_WB_COMPOSE_PRIMARY = 0,
+	DSS_WB_COMPOSE_COPYBIT,
+	DSS_WB_COMPOSE_TYPE_MAX,
+};
+
+enum hisi_fb_pixel_format {
+	HISI_FB_PIXEL_FORMAT_RGB_565 = 0,
+	HISI_FB_PIXEL_FORMAT_RGBX_4444,
+	HISI_FB_PIXEL_FORMAT_RGBA_4444,
+	HISI_FB_PIXEL_FORMAT_RGBX_5551,
+	HISI_FB_PIXEL_FORMAT_RGBA_5551,
+	HISI_FB_PIXEL_FORMAT_RGBX_8888,
+	HISI_FB_PIXEL_FORMAT_RGBA_8888,
+
+	HISI_FB_PIXEL_FORMAT_BGR_565,
+	HISI_FB_PIXEL_FORMAT_BGRX_4444,
+	HISI_FB_PIXEL_FORMAT_BGRA_4444,
+	HISI_FB_PIXEL_FORMAT_BGRX_5551,
+	HISI_FB_PIXEL_FORMAT_BGRA_5551,
+	HISI_FB_PIXEL_FORMAT_BGRX_8888,
+	HISI_FB_PIXEL_FORMAT_BGRA_8888,
+
+	HISI_FB_PIXEL_FORMAT_YUV_422_I,
+
+	/* YUV Semi-planar */
+	HISI_FB_PIXEL_FORMAT_YCbCr_422_SP,	/* NV16 */
+	HISI_FB_PIXEL_FORMAT_YCrCb_422_SP,
+	HISI_FB_PIXEL_FORMAT_YCbCr_420_SP,
+	HISI_FB_PIXEL_FORMAT_YCrCb_420_SP,	/* NV21 */
+
+	/* YUV Planar */
+	HISI_FB_PIXEL_FORMAT_YCbCr_422_P,
+	HISI_FB_PIXEL_FORMAT_YCrCb_422_P,
+	HISI_FB_PIXEL_FORMAT_YCbCr_420_P,
+	HISI_FB_PIXEL_FORMAT_YCrCb_420_P,	/* HISI_FB_PIXEL_FORMAT_YV12 */
+
+	/* YUV Package */
+	HISI_FB_PIXEL_FORMAT_YUYV_422_Pkg,
+	HISI_FB_PIXEL_FORMAT_UYVY_422_Pkg,
+	HISI_FB_PIXEL_FORMAT_YVYU_422_Pkg,
+	HISI_FB_PIXEL_FORMAT_VYUY_422_Pkg,
+	HISI_FB_PIXEL_FORMAT_MAX,
+};
+
+enum hisi_fb_blending {
+	HISI_FB_BLENDING_NONE = 0,
+	HISI_FB_BLENDING_PREMULT = 1,
+	HISI_FB_BLENDING_COVERAGE = 2,
+	HISI_FB_BLENDING_MAX = 3,
+};
+
+enum hisi_fb_transform {
+	HISI_FB_TRANSFORM_NOP = 0x0,
+	/* flip source image horizontally (around the vertical axis) */
+	HISI_FB_TRANSFORM_FLIP_H = 0x01,
+	/* flip source image vertically (around the horizontal axis) */
+	HISI_FB_TRANSFORM_FLIP_V = 0x02,
+	/* rotate source image 90 degrees clockwise */
+	HISI_FB_TRANSFORM_ROT_90 = 0x04,
+	/* rotate source image 180 degrees */
+	HISI_FB_TRANSFORM_ROT_180 = 0x03,
+	/* rotate source image 270 degrees clockwise */
+	HISI_FB_TRANSFORM_ROT_270 = 0x07,
+};
+
+enum dss_csc_mode {
+	DSS_CSC_601_WIDE = 0,
+	DSS_CSC_601_NARROW,
+	DSS_CSC_709_WIDE,
+	DSS_CSC_709_NARROW,
+	DSS_CSC_MOD_MAX,
+};
+
+enum dss_afbc_scramble_mode {
+	DSS_AFBC_SCRAMBLE_NONE = 0,
+	DSS_AFBC_SCRAMBLE_MODE1,
+	DSS_AFBC_SCRAMBLE_MODE2,
+	DSS_AFBC_SCRAMBLE_MODE3,
+	DSS_AFBC_SCRAMBLE_MODE_MAX,
+};
+
+enum dss_chn_idx {
+	DSS_RCHN_NONE = -1,
+	DSS_RCHN_D2 = 0,
+	DSS_RCHN_D3,
+	DSS_RCHN_V0,
+	DSS_RCHN_G0,
+	DSS_RCHN_V1,
+	DSS_RCHN_G1,
+	DSS_RCHN_D0,
+	DSS_RCHN_D1,
+
+	DSS_WCHN_W0,
+	DSS_WCHN_W1,
+
+	DSS_CHN_MAX,
+
+	DSS_RCHN_V2 = DSS_CHN_MAX,
+	DSS_WCHN_W2,
+
+	DSS_COPYBIT_MAX,
+};
+
+enum dss_ovl_idx {
+	DSS_OVL0 = 0,
+	DSS_OVL1,
+	DSS_OVL2,
+	DSS_OVL3,
+	DSS_OVL_IDX_MAX,
+};
+
+/* dss capability priority description */
+#define CAP_1D_SHARPNESS	BIT(13)
+#define CAP_2D_SHARPNESS	BIT(12)
+#define CAP_TILE	BIT(11)
+#define CAP_AFBCD	BIT(10)
+#define CAP_AFBCE	BIT(9)
+#define CAP_YUV_DEINTERLACE	BIT(8)
+#define CAP_YUV_PLANAR	BIT(7)
+#define CAP_YUV_SEMI_PLANAR	BIT(6)
+#define CAP_YUV_PACKAGE	BIT(5)
+#define CAP_SCL	BIT(4)
+#define CAP_ROT	BIT(3)
+#define CAP_PURE_COLOR	BIT(2)
+#define CAP_DIM	BIT(1)
+#define CAP_BASE	BIT(0)
+
+/*this head file to save the structs that both ade and dss will use
+**note: if the left_align is 8,right_align is 8,and w_min is larger than 802,then w_min should be set to 808,
+**make sure that it is 8 align,if w_min is set to 802,there will be an error.left_align,right_align,top_align
+**bottom_align,w_align,h_align,w_min and h_min's valid value should be larger than 0,top_start and bottom_start
+**maybe equal to 0. if it's not surpport partial update, these value should set to invalid value(-1).
+*/
+typedef struct lcd_dirty_region_info {
+	int left_align;
+	int right_align;
+	int top_align;
+	int bottom_align;
+
+	int w_align;
+	int h_align;
+	int w_min;
+	int h_min;
+
+	int top_start;
+	int bottom_start;
+} lcd_dirty_region_info_t;
+
+typedef struct dss_rect {
+	int32_t x;
+	int32_t y;
+	int32_t w;
+	int32_t h;
+} dss_rect_t;
+
+typedef struct dss_rect_ltrb {
+	int32_t left;
+	int32_t top;
+	int32_t right;
+	int32_t bottom;
+} dss_rect_ltrb_t;
+
+typedef struct dss_mmbuf {
+	uint32_t addr;
+	int32_t size;
+} dss_mmbuf_t;
+
+typedef struct dss_img {
+	uint32_t format;
+	uint32_t width;
+	uint32_t height;
+	uint32_t bpp;		/* bytes per pixel */
+	uint32_t buf_size;
+	uint32_t stride;
+	uint32_t stride_plane1;
+	uint32_t stride_plane2;
+	uint64_t phy_addr;
+	uint64_t vir_addr;
+	uint32_t offset_plane1;
+	uint32_t offset_plane2;
+
+	uint64_t afbc_header_addr;
+	uint64_t afbc_payload_addr;
+	uint32_t afbc_header_stride;
+	uint32_t afbc_payload_stride;
+	uint32_t afbc_scramble_mode;
+	uint32_t mmbuf_base;
+	uint32_t mmbuf_size;
+
+	uint32_t mmu_enable;
+	uint32_t csc_mode;
+	uint32_t secure_mode;
+	int32_t shared_fd;
+	uint32_t reserved0;
+} dss_img_t;
+
+typedef struct dss_block_info {
+	int32_t first_tile;
+	int32_t last_tile;
+	uint32_t acc_hscl;
+	uint32_t h_ratio;
+	uint32_t v_ratio;
+	uint32_t h_ratio_arsr2p;
+	uint32_t arsr2p_left_clip;
+	uint32_t both_vscfh_arsr2p_used;
+	dss_rect_t arsr2p_in_rect;
+	uint32_t arsr2p_src_x;
+	uint32_t arsr2p_src_y;
+	uint32_t arsr2p_dst_x;
+	uint32_t arsr2p_dst_y;
+	uint32_t arsr2p_dst_w;
+	int32_t h_v_order;
+} dss_block_info_t;
+
+typedef struct dss_layer {
+	dss_img_t img;
+	dss_rect_t src_rect;
+	dss_rect_t src_rect_mask;
+	dss_rect_t dst_rect;
+	uint32_t transform;
+	int32_t blending;
+	uint32_t glb_alpha;
+	uint32_t color;		/* background color or dim color */
+	int32_t layer_idx;
+	int32_t chn_idx;
+	uint32_t need_cap;
+	int32_t acquire_fence;
+
+	dss_block_info_t block_info;
+} dss_layer_t;
+
+typedef struct dss_wb_layer {
+	dss_img_t dst;
+	dss_rect_t src_rect;
+	dss_rect_t dst_rect;
+	uint32_t transform;
+	int32_t chn_idx;
+	uint32_t need_cap;
+	uint32_t reserved0;
+
+	int32_t acquire_fence;
+	int32_t release_fence;
+} dss_wb_layer_t;
+
+/*
+ ** dss error status
+ */
+#define DSS_PDP_LDI_UNDERFLOW		BIT(0)
+#define DSS_SDP_LDI_UNDERFLOW		BIT(1)
+#define DSS_PDP_SMMU_ERR			BIT(2)
+#define DSS_SDP_SMMU_ERR			BIT(3)
+
+/*
+ ** crc enable status
+ */
+enum dss_crc_enable_status {
+	DSS_CRC_NONE = 0,
+	DSS_CRC_OV_EN = 1,
+	DSS_CRC_LDI_EN,
+	DSS_CRC_SUM_EN,
+};
+
+/*
+ ** sec enable status
+ */
+enum dss_sec_enable_status {
+	DSS_SEC_STOP = 0,
+	DSS_SEC_RUN = 1,
+};
+
+typedef struct dss_crc_info {
+	uint32_t crc_ov_result;
+	uint32_t crc_ldi_result;
+	uint32_t crc_sum_result;
+	uint32_t crc_ov_frm;
+	uint32_t crc_ldi_frm;
+	uint32_t crc_sum_frm;
+
+	uint32_t err_status;
+	uint32_t reserved0;
+} dss_crc_info_t;
+
+enum dss_to_be_continued_type {
+	DSS_LAYER_SERIAL_COMPOSE = 0,
+	DSS_LAYER_PARALLEL_COMPOSE = 1,
+};
+
+/* Max multi-src channel number of the DSS. */
+#define MAX_DSS_SRC_NUM	(7)
+#define MAX_DSS_DST_NUM	(2)
+
+#define HISI_DSS_OV_BLOCK_NUMS	(23)
+
+typedef struct dss_overlay_block {
+	dss_layer_t layer_infos[MAX_DSS_SRC_NUM];
+	dss_rect_t ov_block_rect;
+	uint32_t layer_nums;
+	uint32_t reserved0;
+} dss_overlay_block_t;
+
+typedef struct dss_overlay {
+	dss_wb_layer_t wb_layer_infos[MAX_DSS_DST_NUM];
+	dss_rect_t wb_ov_rect;
+	uint32_t wb_layer_nums;
+	uint32_t wb_compose_type;
+
+	uint64_t ov_block_infos_ptr;
+	uint32_t ov_block_nums;
+	int32_t ovl_idx;
+	uint32_t wb_enable;
+	uint32_t frame_no;
+
+	dss_rect_t dirty_rect;
+
+	struct dss_rect res_updt_rect;
+
+	dss_crc_info_t crc_info;
+	int32_t crc_enable_status;
+	uint32_t sec_enable_status;
+
+	uint32_t to_be_continued;
+	int32_t release_fence;
+} dss_overlay_t;
+
+typedef struct dss_clk_rate {
+	uint64_t dss_pri_clk_rate;
+	uint64_t dss_pclk_dss_rate;
+	uint64_t dss_pclk_pctrl_rate;
+	uint32_t dss_voltage_value;
+} dss_clk_rate_t;
+
+typedef struct ce_algorithm_parameter {
+	int iDiffMaxTH;
+	int iDiffMinTH;
+	int iAlphaMinTH;
+	int iFlatDiffTH;
+	int iBinDiffMaxTH;
+
+	int iDarkPixelMinTH;
+	int iDarkPixelMaxTH;
+	int iDarkAvePixelMinTH;
+	int iDarkAvePixelMaxTH;
+	int iWhitePixelTH;
+	int fweight;
+	int fDarkRatio;
+	int fWhiteRatio;
+
+	int iDarkPixelTH;
+	int fDarkSlopeMinTH;
+	int fDarkSlopeMaxTH;
+	int fDarkRatioMinTH;
+	int fDarkRatioMaxTH;
+
+	int iBrightPixelTH;
+	int fBrightSlopeMinTH;
+	int fBrightSlopeMaxTH;
+	int fBrightRatioMinTH;
+	int fBrightRatioMaxTH;
+
+	int iZeroPos0MaxTH;
+	int iZeroPos1MaxTH;
+
+	int iDarkFMaxTH;
+	int iDarkFMinTH;
+	int iPos0MaxTH;
+	int iPos0MinTH;
+
+	int fKeepRatio;
+} ce_algorithm_parameter_t;
+
+typedef struct ce_parameter {
+	int width;
+	int height;
+	int hist_mode;
+	int mode;
+	int result;
+	uint32_t reserved0;
+	uint32_t *histogram;
+	uint8_t *lut_table;
+	void *service;
+	ce_algorithm_parameter_t ce_alg_param;
+} ce_parameter_t;
+
+typedef struct hiace_alg_parameter {
+	int iGlobalHistBlackPos;
+	int iGlobalHistWhitePos;
+	int iGlobalHistBlackWeight;
+	int iGlobalHistWhiteWeight;
+	int iGlobalHistZeroCutRatio;
+	int iGlobalHistSlopeCutRatio;
+
+	char Classifieresult[1024];
+	int iResultLen;
+
+	int iDoLCE;
+	int iDoSRE;
+	int iDoAPLC;
+
+	int iLaSensorSREOnTH;
+	int iWidth;
+	int iHeight;
+	int bitWidth;
+	int iMode;
+	int iLevel;
+	int ilhist_sft;
+
+	int iMaxLcdLuminance;
+	int iMinLcdLuminance;
+	int iMaxBackLight;
+	int iMinBackLight;
+	int iAmbientLight;
+	int iBackLight;
+	long lTimestamp;
+
+	char chCfgName[512];
+} hiace_alg_parameter_t;
+
+typedef struct hiace_interface_set {
+	int result;
+	unsigned int *lut;
+	int backlight;
+} hiace_interface_set_t;
+
+#endif /*_HISI_DSS_H_*/
diff --git a/drivers/video/fbdev/hisi/dss/hisi_dss_regs_hi3660.h b/drivers/video/fbdev/hisi/dss/hisi_dss_regs_hi3660.h
new file mode 100755
index 000000000000..a5490bb63dc3
--- /dev/null
+++ b/drivers/video/fbdev/hisi/dss/hisi_dss_regs_hi3660.h
@@ -0,0 +1,3164 @@
+/* Copyright (c) 2013-2014, Hisilicon Tech. Co., Ltd. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+ * GNU General Public License for more details.
+ *
+ */
+#ifndef HISI_DSS_REGS_H
+#define HISI_DSS_REGS_H
+
+#include "hisi_fb.h"
+
+/* MACROS */
+#define DSS_WIDTH(width)	((width) - 1)
+#define DSS_HEIGHT(height)	((height) - 1)
+
+#define RES_540P	(960 * 540)
+#define RES_720P	(1280 * 720)
+#define RES_1080P	(1920 * 1080)
+#define RES_1200P	(1920 * 1200)
+#define RES_1440P	(2560 * 1440)
+#define RES_1600P	(2560 * 1600)
+#define RES_4K_PHONE	(3840 * 2160)
+#define RES_4K_PAD	(3840 * 2400)
+
+#define DFC_MAX_CLIP_NUM	(31)
+
+/* for DFS */
+/* 1480 * 144bits */
+#define DFS_TIME	(80)
+#define DFS_TIME_MIN	(50)
+#define DFS_TIME_MIN_4K	(10)
+#define DBUF0_DEPTH	(1408)
+#define DBUF1_DEPTH	(512)
+#define DBUF_WIDTH_BIT	(144)
+
+#define GET_THD_RQOS_IN(max_depth)	((max_depth) * 10 / 100)
+#define GET_THD_RQOS_OUT(max_depth)	((max_depth) * 30 / 100)
+#define GET_THD_WQOS_IN(max_depth)	((max_depth) * 95 / 100)
+#define GET_THD_WQOS_OUT(max_depth)	((max_depth) * 70 / 100)
+#define GET_THD_CG_IN(max_depth)	((max_depth) -1)
+#define GET_THD_CG_OUT(max_depth)	((max_depth) * 70 / 100)
+#define GET_FLUX_REQ_IN(max_depth)	((max_depth) * 50 / 100)
+#define GET_FLUX_REQ_OUT(max_depth)	((max_depth) * 90 / 100)
+#define GET_THD_OTHER_DFS_CG_HOLD(max_depth)	(0x20)
+#define GET_THD_OTHER_WR_WAIT(max_depth)	((max_depth) * 90 / 100)
+
+#define GET_RDMA_ROT_HQOS_ASSERT_LEV(max_depth)	((max_depth) * 30 /100)
+#define GET_RDMA_ROT_HQOS_REMOVE_LEV(max_depth)	((max_depth)* 60 / 100)
+
+enum lcd_orientation {
+	LCD_LANDSCAPE = 0,
+	LCD_PORTRAIT,
+};
+
+enum lcd_format {
+	LCD_RGB888 = 0,
+	LCD_RGB101010,
+	LCD_RGB565,
+};
+
+enum lcd_rgb_order {
+	LCD_RGB = 0,
+	LCD_BGR,
+};
+
+enum dss_addr {
+	DSS_ADDR_PLANE0 = 0,
+	DSS_ADDR_PLANE1,
+	DSS_ADDR_PLANE2,
+};
+
+enum dss_transform {
+	DSS_TRANSFORM_NOP = 0x0,
+	DSS_TRANSFORM_FLIP_H = 0x01,
+	DSS_TRANSFORM_FLIP_V = 0x02,
+	DSS_TRANSFORM_ROT = 0x04,
+};
+
+enum dss_dfc_format {
+	DFC_PIXEL_FORMAT_RGB_565 = 0,
+	DFC_PIXEL_FORMAT_XRGB_4444,
+	DFC_PIXEL_FORMAT_ARGB_4444,
+	DFC_PIXEL_FORMAT_XRGB_5551,
+	DFC_PIXEL_FORMAT_ARGB_5551,
+	DFC_PIXEL_FORMAT_XRGB_8888,
+	DFC_PIXEL_FORMAT_ARGB_8888,
+	DFC_PIXEL_FORMAT_BGR_565,
+	DFC_PIXEL_FORMAT_XBGR_4444,
+	DFC_PIXEL_FORMAT_ABGR_4444,
+	DFC_PIXEL_FORMAT_XBGR_5551,
+	DFC_PIXEL_FORMAT_ABGR_5551,
+	DFC_PIXEL_FORMAT_XBGR_8888,
+	DFC_PIXEL_FORMAT_ABGR_8888,
+
+	DFC_PIXEL_FORMAT_YUV444,
+	DFC_PIXEL_FORMAT_YVU444,
+	DFC_PIXEL_FORMAT_YUYV422,
+	DFC_PIXEL_FORMAT_YVYU422,
+	DFC_PIXEL_FORMAT_VYUY422,
+	DFC_PIXEL_FORMAT_UYVY422,
+};
+
+enum dss_dma_format {
+	DMA_PIXEL_FORMAT_RGB_565 = 0,
+	DMA_PIXEL_FORMAT_ARGB_4444,
+	DMA_PIXEL_FORMAT_XRGB_4444,
+	DMA_PIXEL_FORMAT_ARGB_5551,
+	DMA_PIXEL_FORMAT_XRGB_5551,
+	DMA_PIXEL_FORMAT_ARGB_8888,
+	DMA_PIXEL_FORMAT_XRGB_8888,
+
+	DMA_PIXEL_FORMAT_RESERVED0,
+
+	DMA_PIXEL_FORMAT_YUYV_422_Pkg,
+	DMA_PIXEL_FORMAT_YUV_420_SP_HP,
+	DMA_PIXEL_FORMAT_YUV_420_P_HP,
+	DMA_PIXEL_FORMAT_YUV_422_SP_HP,
+	DMA_PIXEL_FORMAT_YUV_422_P_HP,
+	DMA_PIXEL_FORMAT_AYUV_4444,
+};
+
+enum dss_buf_format {
+	DSS_BUF_LINEAR = 0,
+	DSS_BUF_TILE,
+};
+
+enum dss_blend_mode {
+	DSS_BLEND_CLEAR = 0,
+	DSS_BLEND_SRC,
+	DSS_BLEND_DST,
+	DSS_BLEND_SRC_OVER_DST,
+	DSS_BLEND_DST_OVER_SRC,
+	DSS_BLEND_SRC_IN_DST,
+	DSS_BLEND_DST_IN_SRC,
+	DSS_BLEND_SRC_OUT_DST,
+	DSS_BLEND_DST_OUT_SRC,
+	DSS_BLEND_SRC_ATOP_DST,
+	DSS_BLEND_DST_ATOP_SRC,
+	DSS_BLEND_SRC_XOR_DST,
+	DSS_BLEND_SRC_ADD_DST,
+	DSS_BLEND_FIX_OVER,
+	DSS_BLEND_FIX_PER0,
+	DSS_BLEND_FIX_PER1,
+	DSS_BLEND_FIX_PER2,
+	DSS_BLEND_FIX_PER3,
+	DSS_BLEND_FIX_PER4,
+	DSS_BLEND_FIX_PER5,
+	DSS_BLEND_FIX_PER6,
+	DSS_BLEND_FIX_PER7,
+	DSS_BLEND_FIX_PER8,
+	DSS_BLEND_FIX_PER9,
+	DSS_BLEND_FIX_PER10,
+	DSS_BLEND_FIX_PER11,
+	DSS_BLEND_FIX_PER12,
+	DSS_BLEND_FIX_PER13,
+	DSS_BLEND_FIX_PER14,
+	DSS_BLEND_FIX_PER15,
+	DSS_BLEND_FIX_PER16,
+	DSS_BLEND_FIX_PER17,
+
+	DSS_BLEND_MAX,
+};
+
+enum dss_chn_module {
+	MODULE_MIF_CHN,
+	MODULE_AIF0_CHN,
+	MODULE_AIF1_CHN,
+	MODULE_MCTL_CHN_MUTEX,
+	MODULE_MCTL_CHN_FLUSH_EN,
+	MODULE_MCTL_CHN_OV_OEN,
+	MODULE_MCTL_CHN_STARTY,
+	MODULE_MCTL_CHN_MOD_DBG,
+	MODULE_DMA,
+	MODULE_DFC,
+	MODULE_SCL,
+	MODULE_SCL_LUT,
+	MODULE_ARSR2P,
+	MODULE_ARSR2P_LUT,
+	MODULE_POST_CLIP,
+	MODULE_PCSC,
+	MODULE_CSC,
+	MODULE_CHN_MAX,
+};
+
+enum dss_chn_cap {
+	MODULE_CAP_ROT,
+	MODULE_CAP_SCL,
+	MODULE_CAP_CSC,
+	MODULE_CAP_SHARPNESS_1D,
+	MODULE_CAP_SHARPNESS_2D,
+	MODULE_CAP_CE,
+	MODULE_CAP_AFBCD,
+	MODULE_CAP_AFBCE,
+	MODULE_CAP_YUV_PLANAR,
+	MODULE_CAP_YUV_SEMI_PLANAR,
+	MODULE_CAP_YUV_PACKAGE,
+	MODULE_CAP_MAX,
+};
+
+enum dss_ovl_module {
+	MODULE_OVL_BASE,
+	MODULE_MCTL_BASE,
+	MODULE_OVL_MAX,
+};
+
+enum dss_axi_idx {
+	AXI_CHN0 = 0,
+	AXI_CHN1,
+	AXI_CHN_MAX,
+};
+
+#define AXI0_MAX_DSS_CHN_THRESHOLD	(3)
+#define AXI1_MAX_DSS_CHN_THRESHOLD	(3)
+
+#define DEFAULT_AXI_CLK_RATE0	(120 * 1000000)
+#define DEFAULT_AXI_CLK_RATE1	(240 * 1000000)
+#define DEFAULT_AXI_CLK_RATE2	(360 * 1000000)
+#define DEFAULT_AXI_CLK_RATE3	(480 * 1000000)
+#define DEFAULT_AXI_CLK_RATE4	(667 * 1000000)
+#define DEFAULT_AXI_CLK_RATE5	(800 * 1000000)
+
+enum dss_rdma_idx {
+	DSS_RDMA0 = 0,
+	DSS_RDMA1,
+	DSS_RDMA2,
+	DSS_RDMA3,
+	DSS_RDMA4,
+	DSS_RDMA_MAX,
+};
+
+/*******************************************************************************
+ **
+ */
+
+#define PEREN0	(0x000)
+#define PERDIS0	(0x004)
+#define PEREN2	(0x020)
+#define PERDIS2	(0x024)
+#define PERCLKEN2	(0x028)
+#define PERSTAT2	(0x02C)
+#define PEREN3	(0x030)
+#define PERDIS3	(0x034)
+#define PERCLKEN3	(0x038)
+#define PERSTAT3	(0x03C)
+#define PEREN5	(0x050)
+#define PERDIS5	(0x054)
+#define PERCLKEN5	(0x058)
+#define PERSTAT5	(0x05C)
+#define PERRSTDIS0	(0x064)
+#define PERRSTEN2	(0x078)
+#define PERRSTDIS2	(0x07C)
+#define PERRSTEN3	(0x084)
+#define PERRSTDIS3	(0x088)
+#define PERRSTSTAT3 (0x08c)
+#define PERRSTEN4	(0x090)
+#define PERRSTDIS4	(0x094)
+#define PERRSTSTAT4 (0x098)
+#define CLKDIV3	(0x0B4)
+#define CLKDIV5	(0x0BC)
+#define CLKDIV10	(0x0D0)
+#define CLKDIV18	(0x0F0)
+#define CLKDIV20	(0x0F8)
+#define ISOEN	(0x144)
+#define ISODIS	(0x148)
+#define ISOSTAT	(0x14c)
+#define PERPWREN	(0x150)
+#define PERPWRDIS	(0x154)
+#define PERPWRSTAT 	(0x158)
+#define PERI_AUTODIV8	(0x380)
+#define PERI_AUTODIV9	(0x384)
+#define PERI_AUTODIV10	(0x388)
+
+
+#define NOC_POWER_IDLEREQ	(0x380)
+#define NOC_POWER_IDLEACK	(0x384)
+#define NOC_POWER_IDLE	(0x388)
+
+
+#define SCPWREN 	(0x0D0)
+#define SCPEREN1 (0x040)
+#define SCPERDIS1  (0x044)
+#define SCPERCLKEN1 (0x048)
+#define SCPERRSTDIS1	(0x090)
+#define SCISODIS	(0x0C4)
+#define SCCLKDIV2	(0x258)
+
+
+#define PERI_CTRL23	(0x060)
+#define PERI_CTRL29	(0x078)
+#define PERI_CTRL30	(0x07C)
+#define PERI_CTRL32	(0x084)
+#define PERI_STAT0	(0x094)
+#define PERI_STAT1	(0x098)
+#define PERI_STAT16	(0x0D4)
+
+
+#define PCTRL_DPHYTX_ULPSEXIT1	BIT(4)
+#define PCTRL_DPHYTX_ULPSEXIT0	BIT(3)
+
+
+
+
+
+
+
+
+#define PCTRL_DPHYTX_CTRL1	BIT(1)
+#define PCTRL_DPHYTX_CTRL0	BIT(0)
+
+/*******************************************************************************
+ **
+ */
+
+
+#define BIT_DSS_GLB_INTS	BIT(30)
+#define BIT_MMU_IRPT_S	BIT(29)
+#define BIT_MMU_IRPT_NS	BIT(28)
+#define BIT_DBG_MCTL_INTS	BIT(27)
+#define BIT_DBG_WCH1_INTS	BIT(26)
+#define BIT_DBG_WCH0_INTS	BIT(25)
+#define BIT_DBG_RCH7_INTS	BIT(24)
+#define BIT_DBG_RCH6_INTS	BIT(23)
+#define BIT_DBG_RCH5_INTS	BIT(22)
+#define BIT_DBG_RCH4_INTS	BIT(21)
+#define BIT_DBG_RCH3_INTS	BIT(20)
+#define BIT_DBG_RCH2_INTS	BIT(19)
+#define BIT_DBG_RCH1_INTS	BIT(18)
+#define BIT_DBG_RCH0_INTS	BIT(17)
+#define BIT_ITF0_INTS	BIT(16)
+#define BIT_DPP_INTS	BIT(15)
+#define BIT_CMDLIST13	BIT(14)
+#define BIT_CMDLIST12	BIT(13)
+#define BIT_CMDLIST11	BIT(12)
+#define BIT_CMDLIST10	BIT(11)
+#define BIT_CMDLIST9	BIT(10)
+#define BIT_CMDLIST8	BIT(9)
+#define BIT_CMDLIST7	BIT(8)
+#define BIT_CMDLIST6	BIT(7)
+#define BIT_CMDLIST5	BIT(6)
+#define BIT_CMDLIST4	BIT(5)
+#define BIT_CMDLIST3	BIT(4)
+#define BIT_CMDLIST2	BIT(3)
+#define BIT_CMDLIST1	BIT(2)
+#define BIT_CMDLIST0	BIT(1)
+
+
+
+#define BIT_SDP_DSS_GLB_INTS	BIT(29)
+#define BIT_SDP_MMU_IRPT_S	BIT(28)
+#define BIT_SDP_MMU_IRPT_NS	BIT(27)
+#define BIT_SDP_DBG_MCTL_INTS	BIT(26)
+#define BIT_SDP_DBG_WCH1_INTS	BIT(25)
+#define BIT_SDP_DBG_WCH0_INTS	BIT(24)
+#define BIT_SDP_DBG_RCH7_INTS	BIT(23)
+#define BIT_SDP_DBG_RCH6_INTS	BIT(22)
+#define BIT_SDP_DBG_RCH5_INTS	BIT(21)
+#define BIT_SDP_DBG_RCH4_INTS	BIT(20)
+#define BIT_SDP_DBG_RCH3_INTS	BIT(19)
+#define BIT_SDP_DBG_RCH2_INTS	BIT(18)
+#define BIT_SDP_DBG_RCH1_INTS	BIT(17)
+#define BIT_SDP_DBG_RCH0_INTS	BIT(16)
+#define BIT_SDP_ITF1_INTS	BIT(15)
+#define BIT_SDP_CMDLIST13	BIT(14)
+#define BIT_SDP_CMDLIST12	BIT(13)
+#define BIT_SDP_CMDLIST11	BIT(12)
+#define BIT_SDP_CMDLIST10	BIT(11)
+#define BIT_SDP_CMDLIST9	BIT(10)
+#define BIT_SDP_CMDLIST8	BIT(9)
+#define BIT_SDP_CMDLIST7	BIT(8)
+#define BIT_SDP_CMDLIST6	BIT(7)
+#define BIT_SDP_CMDLIST5	BIT(6)
+#define BIT_SDP_CMDLIST4	BIT(5)
+#define BIT_SDP_CMDLIST3	BIT(4)
+#define BIT_SDP_SDP_CMDLIST2	BIT(3)
+#define BIT_SDP_CMDLIST1	BIT(2)
+#define BIT_SDP_CMDLIST0	BIT(1)
+#define BIT_SDP_RCH_CE_INTS	BIT(0)
+
+
+
+#define BIT_OFF_DSS_GLB_INTS	BIT(31)
+#define BIT_OFF_MMU_IRPT_S	BIT(30)
+#define BIT_OFF_MMU_IRPT_NS	BIT(29)
+#define BIT_OFF_DBG_MCTL_INTS	BIT(28)
+#define BIT_OFF_DBG_WCH1_INTS	BIT(27)
+#define BIT_OFF_DBG_WCH0_INTS	BIT(26)
+#define BIT_OFF_DBG_RCH7_INTS	BIT(25)
+#define BIT_OFF_DBG_RCH6_INTS	BIT(24)
+#define BIT_OFF_DBG_RCH5_INTS	BIT(23)
+#define BIT_OFF_DBG_RCH4_INTS	BIT(22)
+#define BIT_OFF_DBG_RCH3_INTS	BIT(21)
+#define BIT_OFF_DBG_RCH2_INTS	BIT(20)
+#define BIT_OFF_DBG_RCH1_INTS	BIT(19)
+#define BIT_OFF_DBG_RCH0_INTS	BIT(18)
+#define BIT_OFF_WCH1_INTS	BIT(17)
+#define BIT_OFF_WCH0_INTS	BIT(16)
+#define BIT_OFF_WCH0_WCH1_FRM_END_INT	BIT(15)
+#define BIT_OFF_CMDLIST13	BIT(14)
+#define BIT_OFF_CMDLIST12	BIT(13)
+#define BIT_OFF_CMDLIST11	BIT(12)
+#define BIT_OFF_CMDLIST10	BIT(11)
+#define BIT_OFF_CMDLIST9	BIT(10)
+#define BIT_OFF_CMDLIST8	BIT(9)
+#define BIT_OFF_CMDLIST7	BIT(8)
+#define BIT_OFF_CMDLIST6	BIT(7)
+#define BIT_OFF_CMDLIST5	BIT(6)
+#define BIT_OFF_CMDLIST4	BIT(5)
+#define BIT_OFF_CMDLIST3	BIT(4)
+#define BIT_OFF_CMDLIST2	BIT(3)
+#define BIT_OFF_CMDLIST1	BIT(2)
+#define BIT_OFF_CMDLIST0	BIT(1)
+#define BIT_OFF_RCH_CE_INTS	BIT(0)
+
+
+
+#define BIT_OFF_CAM_DBG_WCH2_INTS	BIT(4)
+#define BIT_OFF_CAM_DBG_RCH8_INTS	BIT(3)
+#define BIT_OFF_CAM_WCH2_FRMEND_INTS  BIT(2)
+#define BIT_OFF_CAM_CMDLIST15_INTS	BIT(1)
+#define BIT_OFF_CAM_CMDLIST14_INTS	BIT(0)
+
+
+
+
+
+#define BIT_VACTIVE_CNT	BIT(14)
+#define BIT_DSI_TE_TRI	BIT(13)
+#define BIT_LCD_TE0_PIN	BIT(12)
+#define BIT_LCD_TE1_PIN	BIT(11)
+#define BIT_VACTIVE1_END	BIT(10)
+#define BIT_VACTIVE1_START	BIT(9)
+#define BIT_VACTIVE0_END	BIT(8)
+#define BIT_VACTIVE0_START	BIT(7)
+#define BIT_VFRONTPORCH	BIT(6)
+#define BIT_VBACKPORCH	BIT(5)
+#define BIT_VSYNC	BIT(4)
+#define BIT_VFRONTPORCH_END	BIT(3)
+#define BIT_LDI_UNFLOW	BIT(2)
+#define BIT_FRM_END	BIT(1)
+#define BIT_FRM_START	BIT(0)
+
+
+#define BIT_CTL_FLUSH_EN	BIT(21)
+#define BIT_SCF_FLUSH_EN	BIT(19)
+#define BIT_DPP0_FLUSH_EN	BIT(18)
+#define BIT_DBUF1_FLUSH_EN	BIT(17)
+#define BIT_DBUF0_FLUSH_EN	BIT(16)
+#define BIT_OV3_FLUSH_EN	BIT(15)
+#define BIT_OV2_FLUSH_EN	BIT(14)
+#define BIT_OV1_FLUSH_EN	BIT(13)
+#define BIT_OV0_FLUSH_EN	BIT(12)
+#define BIT_WB1_FLUSH_EN	BIT(11)
+#define BIT_WB0_FLUSH_EN	BIT(10)
+#define BIT_DMA3_FLUSH_EN	BIT(9)
+#define BIT_DMA2_FLUSH_EN	BIT(8)
+#define BIT_DMA1_FLUSH_EN	BIT(7)
+#define BIT_DMA0_FLUSH_EN	BIT(6)
+#define BIT_RGB1_FLUSH_EN	BIT(4)
+#define BIT_RGB0_FLUSH_EN	BIT(3)
+#define BIT_VIG1_FLUSH_EN	BIT(1)
+#define BIT_VIG0_FLUSH_EN	BIT(0)
+
+
+
+#define BIT_BUS_DBG_INT	BIT(5)
+#define BIT_CRC_SUM_INT	BIT(4)
+#define BIT_CRC_ITF1_INT	BIT(3)
+#define BIT_CRC_ITF0_INT	BIT(2)
+#define BIT_CRC_OV1_INT	BIT(1)
+#define BIT_CRC_OV0_INT	BIT(0)
+
+
+#define BIT_SBL_SEND_FRAME_OUT	BIT(19)
+#define BIT_SBL_STOP_FRAME_OUT	BIT(18)
+#define BIT_SBL_BACKLIGHT_OUT	BIT(17)
+#define BIT_SBL_DARKENH_OUT		BIT(16)
+#define BIT_SBL_BRIGHTPTR_OUT	BIT(15)
+#define BIT_STRENGTH_INROI_OUT	BIT(14)
+#define BIT_STRENGTH_OUTROI_OUT	BIT(13)
+#define BIT_DONE_OUT			BIT(12)
+#define BIT_PPROC_DONE_OUT		BIT(11)
+
+#define BIT_HIACE_IND	BIT(8)
+#define BIT_STRENGTH_INTP	BIT(7)
+#define BIT_BACKLIGHT_INTP	BIT(6)
+#define BIT_CE_END_IND	BIT(5)
+#define BIT_CE_CANCEL_IND	BIT(4)
+#define BIT_CE_LUT1_RW_COLLIDE_IND	BIT(3)
+#define BIT_CE_LUT0_RW_COLLIDE_IND	BIT(2)
+#define BIT_CE_HIST1_RW_COLLIDE_IND	BIT(1)
+#define BIT_CE_HIST0_RW_COLLIDE_IND	BIT(0)
+
+/*******************************************************************************
+ ** MODULE BASE ADDRESS
+ */
+
+#define DSS_MIPI_DSI0_OFFSET	(0x00001000)
+#define DSS_MIPI_DSI1_OFFSET	(0x00001400)
+
+#define DSS_GLB0_OFFSET	(0x12000)
+
+#define DSS_DBG_OFFSET	(0x11000)
+
+
+#define DSS_CMDLIST_OFFSET	(0x2000)
+
+
+#define DSS_SMMU_OFFSET	(0x8000)
+
+
+#define DSS_VBIF0_AIF	(0x7000)
+#define DSS_VBIF1_AIF	(0x9000)
+
+
+#define DSS_MIF_OFFSET	(0xA000)
+
+
+#define DSS_MCTRL_SYS_OFFSET	(0x10000)
+
+
+#define DSS_MCTRL_CTL0_OFFSET	(0x10800)
+#define DSS_MCTRL_CTL1_OFFSET	(0x10900)
+#define DSS_MCTRL_CTL2_OFFSET	(0x10A00)
+#define DSS_MCTRL_CTL3_OFFSET	(0x10B00)
+#define DSS_MCTRL_CTL4_OFFSET	(0x10C00)
+#define DSS_MCTRL_CTL5_OFFSET	(0x10D00)
+
+
+#define DSS_RCH_VG0_DMA_OFFSET	(0x20000)
+#define DSS_RCH_VG0_DFC_OFFSET (0x20100)
+#define DSS_RCH_VG0_SCL_OFFSET	(0x20200)
+#define DSS_RCH_VG0_ARSR_OFFSET	(0x20300)
+#define DSS_RCH_VG0_POST_CLIP_OFFSET	(0x203A0)
+#define DSS_RCH_VG0_PCSC_OFFSET	(0x20400)
+#define DSS_RCH_VG0_CSC_OFFSET	(0x20500)
+#define DSS_RCH_VG0_DEBUG_OFFSET	(0x20600)
+#define DSS_RCH_VG0_VPP_OFFSET	(0x20700)
+#define DSS_RCH_VG0_DMA_BUF_OFFSET	(0x20800)
+#define DSS_RCH_VG0_AFBCD_OFFSET	(0x20900)
+#define DSS_RCH_VG0_REG_DEFAULT_OFFSET	(0x20A00)
+#define DSS_RCH_VG0_SCL_LUT_OFFSET	(0x21000)
+#define DSS_RCH_VG0_ARSR_LUT_OFFSET	(0x25000)
+
+#define DSS_RCH_VG1_DMA_OFFSET	(0x28000)
+#define DSS_RCH_VG1_DFC_OFFSET (0x28100)
+#define DSS_RCH_VG1_SCL_OFFSET	(0x28200)
+#define DSS_RCH_VG1_POST_CLIP_OFFSET	(0x283A0)
+#define DSS_RCH_VG1_CSC_OFFSET	(0x28500)
+#define DSS_RCH_VG1_DEBUG_OFFSET	(0x28600)
+#define DSS_RCH_VG1_VPP_OFFSET	(0x28700)
+#define DSS_RCH_VG1_DMA_BUF_OFFSET	(0x28800)
+#define DSS_RCH_VG1_AFBCD_OFFSET	(0x28900)
+#define DSS_RCH_VG1_REG_DEFAULT_OFFSET	(0x28A00)
+#define DSS_RCH_VG1_SCL_LUT_OFFSET	(0x29000)
+
+#define DSS_RCH_VG2_DMA_OFFSET	(0x30000)
+#define DSS_RCH_VG2_DFC_OFFSET (0x30100)
+#define DSS_RCH_VG2_SCL_OFFSET	(0x30200)
+#define DSS_RCH_VG2_POST_CLIP_OFFSET	(0x303A0)
+#define DSS_RCH_VG2_CSC_OFFSET	(0x30500)
+#define DSS_RCH_VG2_DEBUG_OFFSET	(0x30600)
+#define DSS_RCH_VG2_VPP_OFFSET	(0x30700)
+#define DSS_RCH_VG2_DMA_BUF_OFFSET	(0x30800)
+#define DSS_RCH_VG2_AFBCD_OFFSET	(0x30900)
+#define DSS_RCH_VG2_REG_DEFAULT_OFFSET	(0x30A00)
+#define DSS_RCH_VG2_SCL_LUT_OFFSET	(0x31000)
+
+
+#define DSS_RCH_G0_DMA_OFFSET	(0x38000)
+#define DSS_RCH_G0_DFC_OFFSET	(0x38100)
+#define DSS_RCH_G0_SCL_OFFSET	(0x38200)
+#define DSS_RCH_G0_POST_CLIP_OFFSET (0x383A0)
+#define DSS_RCH_G0_CSC_OFFSET (0x38500)
+#define DSS_RCH_G0_DEBUG_OFFSET (0x38600)
+#define DSS_RCH_G0_DMA_BUF_OFFSET (0x38800)
+#define DSS_RCH_G0_AFBCD_OFFSET (0x38900)
+#define DSS_RCH_G0_REG_DEFAULT_OFFSET (0x38A00)
+
+#define DSS_RCH_G1_DMA_OFFSET	(0x40000)
+#define DSS_RCH_G1_DFC_OFFSET	(0x40100)
+#define DSS_RCH_G1_SCL_OFFSET	(0x40200)
+#define DSS_RCH_G1_POST_CLIP_OFFSET (0x403A0)
+#define DSS_RCH_G1_CSC_OFFSET (0x40500)
+#define DSS_RCH_G1_DEBUG_OFFSET (0x40600)
+#define DSS_RCH_G1_DMA_BUF_OFFSET (0x40800)
+#define DSS_RCH_G1_AFBCD_OFFSET (0x40900)
+#define DSS_RCH_G1_REG_DEFAULT_OFFSET (0x40A00)
+
+
+#define DSS_RCH_D2_DMA_OFFSET	(0x50000)
+#define DSS_RCH_D2_DFC_OFFSET	(0x50100)
+#define DSS_RCH_D2_CSC_OFFSET	(0x50500)
+#define DSS_RCH_D2_DEBUG_OFFSET	(0x50600)
+#define DSS_RCH_D2_DMA_BUF_OFFSET	(0x50800)
+#define DSS_RCH_D2_AFBCD_OFFSET	(0x50900)
+
+#define DSS_RCH_D3_DMA_OFFSET	(0x51000)
+#define DSS_RCH_D3_DFC_OFFSET	(0x51100)
+#define DSS_RCH_D3_CSC_OFFSET	(0x51500)
+#define DSS_RCH_D3_DEBUG_OFFSET	(0x51600)
+#define DSS_RCH_D3_DMA_BUF_OFFSET	(0x51800)
+#define DSS_RCH_D3_AFBCD_OFFSET	(0x51900)
+
+#define DSS_RCH_D0_DMA_OFFSET	(0x52000)
+#define DSS_RCH_D0_DFC_OFFSET	(0x52100)
+#define DSS_RCH_D0_CSC_OFFSET	(0x52500)
+#define DSS_RCH_D0_DEBUG_OFFSET	(0x52600)
+#define DSS_RCH_D0_DMA_BUF_OFFSET	(0x52800)
+#define DSS_RCH_D0_AFBCD_OFFSET	(0x52900)
+
+#define DSS_RCH_D1_DMA_OFFSET	(0x53000)
+#define DSS_RCH_D1_DFC_OFFSET	(0x53100)
+#define DSS_RCH_D1_CSC_OFFSET	(0x53500)
+#define DSS_RCH_D1_DEBUG_OFFSET	(0x53600)
+#define DSS_RCH_D1_DMA_BUF_OFFSET	(0x53800)
+#define DSS_RCH_D1_AFBCD_OFFSET	(0x53900)
+
+
+#define DSS_WCH0_DMA_OFFSET	(0x5A000)
+#define DSS_WCH0_DFC_OFFSET	(0x5A100)
+#define DSS_WCH0_CSC_OFFSET	(0x5A500)
+#define DSS_WCH0_ROT_OFFSET	(0x5A500)
+#define DSS_WCH0_DEBUG_OFFSET	(0x5A600)
+#define DSS_WCH0_DMA_BUFFER_OFFSET	(0x5A800)
+#define DSS_WCH0_AFBCE_OFFSET	(0x5A900)
+
+#define DSS_WCH1_DMA_OFFSET	(0x5C000)
+#define DSS_WCH1_DFC_OFFSET	(0x5C100)
+#define DSS_WCH1_CSC_OFFSET	(0x5C500)
+#define DSS_WCH1_ROT_OFFSET	(0x5C500)
+#define DSS_WCH1_DEBUG_OFFSET	(0x5C600)
+#define DSS_WCH1_DMA_BUFFER_OFFSET	(0x5C800)
+#define DSS_WCH1_AFBCE_OFFSET	(0x5C900)
+
+#define DSS_WCH2_DMA_OFFSET	(0x5E000)
+#define DSS_WCH2_DFC_OFFSET	(0x5E100)
+#define DSS_WCH2_CSC_OFFSET	(0x5E500)
+#define DSS_WCH2_ROT_OFFSET	(0x5E500)
+#define DSS_WCH2_DEBUG_OFFSET	(0x5E600)
+#define DSS_WCH2_DMA_BUFFER_OFFSET	(0x5E800)
+#define DSS_WCH2_AFBCE_OFFSET	(0x5E900)
+
+
+#define DSS_OVL0_OFFSET	(0x60000)
+#define DSS_OVL1_OFFSET	(0x60400)
+#define DSS_OVL2_OFFSET	(0x60800)
+#define DSS_OVL3_OFFSET	(0x60C00)
+
+
+#define DSS_DBUF0_OFFSET	(0x6D000)
+#define DSS_DBUF1_OFFSET	(0x6E000)
+
+
+#define DSS_HI_ACE_OFFSET	(0x6F000)
+
+
+#define DSS_DPP_OFFSET	(0x70000)
+#define DSS_TOP_OFFSET	(0x70000)
+#define DSS_DPP_COLORBAR_OFFSET	(0x70100)
+#define DSS_DPP_DITHER_OFFSET	(0x70200)
+#define DSS_DPP_CSC_RGB2YUV10B_OFFSET	(0x70300)
+#define DSS_DPP_CSC_YUV2RGB10B_OFFSET	(0x70400)
+#define DSS_DPP_DEGAMA_OFFSET	(0x70500)
+#define DSS_DPP_GAMA_OFFSET	(0x70600)
+#define DSS_DPP_ACM_OFFSET	(0x70700)
+#define DSS_DPP_ACE_OFFSET	(0x70800)
+#define DSS_DPP_LCP_OFFSET	(0x70900)
+#define DSS_DPP_ARSR1P_OFFSET	(0x70A00)
+#define DSS_DPP_BITEXT0_OFFSET	(0x70B00)
+#define DSS_DPP_GAMA_LUT_OFFSET	(0x71000)
+#define DSS_DPP_ACM_LUT_OFFSET	(0x72000)
+#define DSS_DPP_LCP_LUT_OFFSET	(0x73000)
+#define DSS_DPP_ACE_LUT_OFFSET	(0x79000)
+#define DSS_DPP_ARSR1P_LUT_OFFSET	(0x7B000)
+
+
+#define DSS_POST_SCF_OFFSET	DSS_DPP_ARSR1P_OFFSET
+#define DSS_POST_SCF_LUT_OFFSET	DSS_DPP_ARSR1P_LUT_OFFSET
+
+#define DSS_DPP_SBL_OFFSET	(0x7C000)
+#define DSS_LDI0_OFFSET	(0x7D000)
+#define DSS_IFBC_OFFSET	(0x7D800)
+#define DSS_DSC_OFFSET	(0x7DC00)
+#define DSS_LDI1_OFFSET	(0x7E000)
+
+/*******************************************************************************
+ ** GLB
+ */
+#define GLB_DSS_TAG	 (DSS_GLB0_OFFSET + 0x0000)
+
+#define GLB_APB_CTL	 (DSS_GLB0_OFFSET + 0x0004)
+
+#define GLB_DSS_AXI_RST_EN	(DSS_GLB0_OFFSET + 0x0118)
+#define GLB_DSS_APB_RST_EN	(DSS_GLB0_OFFSET + 0x011C)
+#define GLB_DSS_CORE_RST_EN	(DSS_GLB0_OFFSET + 0x0120)
+#define GLB_PXL0_DIV2_RST_EN	(DSS_GLB0_OFFSET + 0x0124)
+#define GLB_PXL0_DIV4_RST_EN	(DSS_GLB0_OFFSET + 0x0128)
+#define GLB_PXL0_RST_EN	(DSS_GLB0_OFFSET + 0x012C)
+#define GLB_PXL0_DSI_RST_EN	(DSS_GLB0_OFFSET + 0x0130)
+#define GLB_DSS_PXL1_RST_EN	(DSS_GLB0_OFFSET + 0x0134)
+#define GLB_MM_AXI_CLK_RST_EN	(DSS_GLB0_OFFSET + 0x0138)
+#define GLB_AFBCD0_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0140)
+#define GLB_AFBCD1_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0144)
+#define GLB_AFBCD2_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0148)
+#define GLB_AFBCD3_IP_RST_EN	(DSS_GLB0_OFFSET + 0x014C)
+#define GLB_AFBCD4_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0150)
+#define GLB_AFBCD5_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0154)
+#define GLB_AFBCD6_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0158)
+#define GLB_AFBCD7_IP_RST_EN	(DSS_GLB0_OFFSET + 0x015C)
+#define GLB_AFBCE0_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0160)
+#define GLB_AFBCE1_IP_RST_EN	(DSS_GLB0_OFFSET + 0x0164)
+
+
+#define GLB_MCU_PDP_INTS	(DSS_GLB0_OFFSET + 0x20C)
+#define GLB_MCU_PDP_INT_MSK	(DSS_GLB0_OFFSET + 0x210)
+#define GLB_MCU_SDP_INTS	(DSS_GLB0_OFFSET + 0x214)
+#define GLB_MCU_SDP_INT_MSK	(DSS_GLB0_OFFSET + 0x218)
+#define GLB_MCU_OFF_INTS	(DSS_GLB0_OFFSET + 0x21C)
+#define GLB_MCU_OFF_INT_MSK	(DSS_GLB0_OFFSET + 0x220)
+#define GLB_MCU_OFF_CAM_INTS	(DSS_GLB0_OFFSET + 0x2B4)
+#define GLB_MCU_OFF_CAM_INT_MSK	(DSS_GLB0_OFFSET + 0x2B8)
+#define GLB_CPU_PDP_INTS	(DSS_GLB0_OFFSET + 0x224)
+#define GLB_CPU_PDP_INT_MSK	(DSS_GLB0_OFFSET + 0x228)
+#define GLB_CPU_SDP_INTS	(DSS_GLB0_OFFSET + 0x22C)
+#define GLB_CPU_SDP_INT_MSK	(DSS_GLB0_OFFSET + 0x230)
+#define GLB_CPU_OFF_INTS	(DSS_GLB0_OFFSET + 0x234)
+#define GLB_CPU_OFF_INT_MSK	(DSS_GLB0_OFFSET + 0x238)
+#define GLB_CPU_OFF_CAM_INTS	(DSS_GLB0_OFFSET + 0x2AC)
+#define GLB_CPU_OFF_CAM_INT_MSK	(DSS_GLB0_OFFSET + 0x2B0)
+
+
+#define GLB_MODULE_CLK_SEL	(DSS_GLB0_OFFSET + 0x0300)
+#define GLB_MODULE_CLK_EN	(DSS_GLB0_OFFSET + 0x0304)
+
+#define GLB_GLB0_DBG_SEL	(DSS_GLB0_OFFSET + 0x310)
+#define GLB_GLB1_DBG_SEL	(DSS_GLB0_OFFSET + 0x314)
+#define GLB_DBG_IRQ_CPU	(DSS_GLB0_OFFSET + 0x320)
+#define GLB_DBG_IRQ_MCU	(DSS_GLB0_OFFSET + 0x324)
+
+#define GLB_TP_SEL	(DSS_GLB0_OFFSET + 0x0400)
+#define GLB_CRC_DBG_LDI0	(DSS_GLB0_OFFSET + 0x0404)
+#define GLB_CRC_DBG_LDI1	(DSS_GLB0_OFFSET + 0x0408)
+#define GLB_CRC_LDI0_EN	(DSS_GLB0_OFFSET + 0x040C)
+#define GLB_CRC_LDI0_FRM	(DSS_GLB0_OFFSET + 0x0410)
+#define GLB_CRC_LDI1_EN	(DSS_GLB0_OFFSET + 0x0414)
+#define GLB_CRC_LDI1_FRM	(DSS_GLB0_OFFSET + 0x0418)
+
+#define GLB_DSS_MEM_CTRL	(DSS_GLB0_OFFSET + 0x0600)
+#define GLB_DSS_PM_CTRL	(DSS_GLB0_OFFSET + 0x0604)
+
+/*******************************************************************************
+ ** DBG
+ */
+#define DBG_CRC_DBG_OV0	(0x0000)
+#define DBG_CRC_DBG_OV1	(0x0004)
+#define DBG_CRC_DBG_SUM	(0x0008)
+#define DBG_CRC_OV0_EN	(0x000C)
+#define DBG_DSS_GLB_DBG_O	(0x0010)
+#define DBG_DSS_GLB_DBG_I	(0x0014)
+#define DBG_CRC_OV0_FRM	(0x0018)
+#define DBG_CRC_OV1_EN	(0x001C)
+#define DBG_CRC_OV1_FRM	(0x0020)
+#define DBG_CRC_SUM_EN	(0x0024)
+#define DBG_CRC_SUM_FRM	(0x0028)
+
+#define DBG_MCTL_INTS	(0x023C)
+#define DBG_MCTL_INT_MSK	(0x0240)
+#define DBG_WCH0_INTS	(0x0244)
+#define DBG_WCH0_INT_MSK	(0x0248)
+#define DBG_WCH1_INTS	(0x024C)
+#define DBG_WCH1_INT_MSK	(0x0250)
+#define DBG_RCH0_INTS	(0x0254)
+#define DBG_RCH0_INT_MSK	(0x0258)
+#define DBG_RCH1_INTS	(0x025C)
+#define DBG_RCH1_INT_MSK	(0x0260)
+#define DBG_RCH2_INTS	(0x0264)
+#define DBG_RCH2_INT_MSK	(0x0268)
+#define DBG_RCH3_INTS	(0x026C)
+#define DBG_RCH3_INT_MSK	(0x0270)
+#define DBG_RCH4_INTS	(0x0274)
+#define DBG_RCH4_INT_MSK	(0x0278)
+#define DBG_RCH5_INTS	(0x027C)
+#define DBG_RCH5_INT_MSK	(0x0280)
+#define DBG_RCH6_INTS	(0x0284)
+#define DBG_RCH6_INT_MSK	(0x0288)
+#define DBG_RCH7_INTS	(0x028C)
+#define DBG_RCH7_INT_MSK	(0x0290)
+#define DBG_DSS_GLB_INTS	(0x0294)
+#define DBG_DSS_GLB_INT_MSK	(0x0298)
+#define DBG_WCH2_INTS	(0x029C)
+#define DBG_WCH2_INT_MSK	(0x02A0)
+#define DBG_RCH8_INTS	(0x02A4)
+#define DBG_RCH8_INT_MSK	(0x02A8)
+
+/*******************************************************************************
+ ** CMDLIST
+ */
+
+#define CMDLIST_CH0_PENDING_CLR	(0x0000)
+#define CMDLIST_CH0_CTRL	(0x0004)
+#define CMDLIST_CH0_STATUS	(0x0008)
+#define CMDLIST_CH0_STAAD	(0x000C)
+#define CMDLIST_CH0_CURAD	(0x0010)
+#define CMDLIST_CH0_INTE	(0x0014)
+#define CMDLIST_CH0_INTC	(0x0018)
+#define CMDLIST_CH0_INTS	(0x001C)
+#define CMDLIST_CH0_SCENE	(0x0020)
+#define CMDLIST_CH0_DBG	(0x0028)
+
+#define CMDLIST_DBG	(0x0700)
+#define CMDLIST_BUF_DBG_EN	(0x0704)
+#define CMDLIST_BUF_DBG_CNT_CLR	(0x0708)
+#define CMDLIST_BUF_DBG_CNT	(0x070C)
+#define CMDLIST_TIMEOUT_TH	(0x0710)
+#define CMDLIST_START	(0x0714)
+#define CMDLIST_ADDR_MASK_EN	(0x0718)
+#define CMDLIST_ADDR_MASK_DIS	(0x071C)
+#define CMDLIST_ADDR_MASK_STATUS	(0x0720)
+#define CMDLIST_TASK_CONTINUE	(0x0724)
+#define CMDLIST_TASK_STATUS	(0x0728)
+#define CMDLIST_CTRL	(0x072C)
+#define CMDLIST_SECU	(0x0730)
+#define CMDLIST_INTS	(0x0734)
+#define CMDLIST_SWRST	(0x0738)
+#define CMD_MEM_CTRL	(0x073C)
+#define CMD_CLK_SEL		(0x0740)
+#define CMD_CLK_EN	(0x0744)
+
+#define HISI_DSS_MIN_ROT_AFBCE_BLOCK_SIZE (256)
+#define HISI_DSS_MAX_ROT_AFBCE_BLOCK_SIZE (480)
+
+
+#define BIT_CMDLIST_CH_TASKDONE_INTS	    BIT(7)
+#define BIT_CMDLIST_CH_TIMEOUT_INTS	    BIT(6)
+#define BIT_CMDLIST_CH_BADCMD_INTS	    BIT(5)
+#define BIT_CMDLIST_CH_START_INTS	           BIT(4)
+#define BIT_CMDLIST_CH_PENDING_INTS	    BIT(3)
+#define BIT_CMDLIST_CH_AXIERR_INTS	    BIT(2)
+#define BIT_CMDLIST_CH_ALLDONE_INTS	    BIT(1)
+#define BIT_CMDLIST_CH_ONEDONE_INTS	    BIT(0)
+
+#define BIT_CMDLIST_CH15_INTS	BIT(15)
+#define BIT_CMDLIST_CH14_INTS	BIT(14)
+#define BIT_CMDLIST_CH13_INTS	BIT(13)
+#define BIT_CMDLIST_CH12_INTS	BIT(12)
+#define BIT_CMDLIST_CH11_INTS	BIT(11)
+#define BIT_CMDLIST_CH10_INTS	BIT(10)
+#define BIT_CMDLIST_CH9_INTS	BIT(9)
+#define BIT_CMDLIST_CH8_INTS	BIT(8)
+#define BIT_CMDLIST_CH7_INTS	BIT(7)
+#define BIT_CMDLIST_CH6_INTS	BIT(6)
+#define BIT_CMDLIST_CH5_INTS	BIT(5)
+#define BIT_CMDLIST_CH4_INTS	BIT(4)
+#define BIT_CMDLIST_CH3_INTS	BIT(3)
+#define BIT_CMDLIST_CH2_INTS	BIT(2)
+#define BIT_CMDLIST_CH1_INTS	BIT(1)
+#define BIT_CMDLIST_CH0_INTS	BIT(0)
+
+/*******************************************************************************
+ ** AIF
+ */
+#define AIF0_CH0_OFFSET	(DSS_VBIF0_AIF + 0x00)
+#define AIF0_CH0_ADD_OFFSET	(DSS_VBIF0_AIF + 0x04)
+#define AIF0_CH1_OFFSET	(DSS_VBIF0_AIF + 0x20)
+#define AIF0_CH1_ADD_OFFSET	(DSS_VBIF0_AIF + 0x24)
+#define AIF0_CH2_OFFSET	(DSS_VBIF0_AIF + 0x40)
+#define AIF0_CH2_ADD_OFFSET	(DSS_VBIF0_AIF + 0x44)
+#define AIF0_CH3_OFFSET	(DSS_VBIF0_AIF + 0x60)
+#define AIF0_CH3_ADD_OFFSET	(DSS_VBIF0_AIF + 0x64)
+#define AIF0_CH4_OFFSET	(DSS_VBIF0_AIF + 0x80)
+#define AIF0_CH4_ADD_OFFSET	(DSS_VBIF0_AIF + 0x84)
+#define AIF0_CH5_OFFSET	(DSS_VBIF0_AIF + 0xA0)
+#define AIF0_CH5_ADD_OFFSET	(DSS_VBIF0_AIF + 0xa4)
+#define AIF0_CH6_OFFSET	(DSS_VBIF0_AIF + 0xC0)
+#define AIF0_CH6_ADD_OFFSET	(DSS_VBIF0_AIF + 0xc4)
+#define AIF0_CH7_OFFSET	(DSS_VBIF0_AIF + 0xE0)
+#define AIF0_CH7_ADD_OFFSET	(DSS_VBIF0_AIF + 0xe4)
+#define AIF0_CH8_OFFSET	(DSS_VBIF0_AIF + 0x100)
+#define AIF0_CH8_ADD_OFFSET	(DSS_VBIF0_AIF + 0x104)
+#define AIF0_CH9_OFFSET	(DSS_VBIF0_AIF + 0x120)
+#define AIF0_CH9_ADD_OFFSET	(DSS_VBIF0_AIF + 0x124)
+#define AIF0_CH10_OFFSET	(DSS_VBIF0_AIF + 0x140)
+#define AIF0_CH10_ADD_OFFSET	(DSS_VBIF0_AIF + 0x144)
+#define AIF0_CH11_OFFSET	(DSS_VBIF0_AIF + 0x160)
+#define AIF0_CH11_ADD_OFFSET	(DSS_VBIF0_AIF + 0x164)
+#define AIF0_CH12_OFFSET	(DSS_VBIF0_AIF + 0x180)
+#define AIF0_CH12_ADD_OFFSET	(DSS_VBIF0_AIF + 0x184)
+
+#define AIF1_CH0_OFFSET	(DSS_VBIF1_AIF + 0x00)
+#define AIF1_CH0_ADD_OFFSET	(DSS_VBIF1_AIF + 0x04)
+#define AIF1_CH1_OFFSET	(DSS_VBIF1_AIF + 0x20)
+#define AIF1_CH1_ADD_OFFSET	(DSS_VBIF1_AIF + 0x24)
+#define AIF1_CH2_OFFSET	(DSS_VBIF1_AIF + 0x40)
+#define AIF1_CH2_ADD_OFFSET	(DSS_VBIF1_AIF + 0x44)
+#define AIF1_CH3_OFFSET	(DSS_VBIF1_AIF + 0x60)
+#define AIF1_CH3_ADD_OFFSET	(DSS_VBIF1_AIF + 0x64)
+#define AIF1_CH4_OFFSET	(DSS_VBIF1_AIF + 0x80)
+#define AIF1_CH4_ADD_OFFSET	(DSS_VBIF1_AIF + 0x84)
+#define AIF1_CH5_OFFSET	(DSS_VBIF1_AIF + 0xA0)
+#define AIF1_CH5_ADD_OFFSET	(DSS_VBIF1_AIF + 0xa4)
+#define AIF1_CH6_OFFSET	(DSS_VBIF1_AIF + 0xC0)
+#define AIF1_CH6_ADD_OFFSET	(DSS_VBIF1_AIF + 0xc4)
+#define AIF1_CH7_OFFSET	(DSS_VBIF1_AIF + 0xE0)
+#define AIF1_CH7_ADD_OFFSET	(DSS_VBIF1_AIF + 0xe4)
+#define AIF1_CH8_OFFSET	(DSS_VBIF1_AIF + 0x100)
+#define AIF1_CH8_ADD_OFFSET	(DSS_VBIF1_AIF + 0x104)
+#define AIF1_CH9_OFFSET	(DSS_VBIF1_AIF + 0x120)
+#define AIF1_CH9_ADD_OFFSET	(DSS_VBIF1_AIF + 0x124)
+#define AIF1_CH10_OFFSET	(DSS_VBIF1_AIF + 0x140)
+#define AIF1_CH10_ADD_OFFSET	(DSS_VBIF1_AIF + 0x144)
+#define AIF1_CH11_OFFSET	(DSS_VBIF1_AIF + 0x160)
+#define AIF1_CH11_ADD_OFFSET	(DSS_VBIF1_AIF + 0x164)
+#define AIF1_CH12_OFFSET	(DSS_VBIF1_AIF + 0x180)
+#define AIF1_CH12_ADD_OFFSET	(DSS_VBIF1_AIF + 0x184)
+
+/* aif dmax */
+
+#define AIF_CH_CTL	(0x0000)
+
+#define AIF_CH_CTL_ADD (0x0004)
+
+
+/* aif common */
+#define AXI0_RID_MSK0	(0x0800)
+#define AXI0_RID_MSK1	(0x0804)
+#define AXI0_WID_MSK	(0x0808)
+#define AXI0_R_QOS_MAP	(0x080c)
+#define AXI1_RID_MSK0	(0x0810)
+#define AXI1_RID_MSK1	(0x0814)
+#define AXI1_WID_MSK	(0x0818)
+#define AXI1_R_QOS_MAP	(0x081c)
+#define AIF_CLK_SEL0	(0x0820)
+#define AIF_CLK_SEL1	(0x0824)
+#define AIF_CLK_EN0	(0x0828)
+#define AIF_CLK_EN1	(0x082c)
+#define MONITOR_CTRL	(0x0830)
+#define MONITOR_TIMER_INI	(0x0834)
+#define DEBUG_BUF_BASE	(0x0838)
+#define DEBUG_CTRL	(0x083C)
+#define AIF_SHADOW_READ	(0x0840)
+#define AIF_MEM_CTRL	(0x0844)
+#define AIF_MONITOR_EN	(0x0848)
+#define AIF_MONITOR_CTRL	(0x084C)
+#define AIF_MONITOR_SAMPLE_MUN	(0x0850)
+#define AIF_MONITOR_SAMPLE_TIME	(0x0854)
+#define AIF_MONITOR_SAMPLE_FLOW	(0x0858)
+
+/* aif debug */
+#define AIF_MONITOR_READ_DATA	(0x0880)
+#define AIF_MONITOR_WRITE_DATA	(0x0884)
+#define AIF_MONITOR_WINDOW_CYCLE	(0x0888)
+#define AIF_MONITOR_WBURST_CNT	(0x088C)
+#define AIF_MONITOR_MIN_WR_CYCLE	(0x0890)
+#define AIF_MONITOR_MAX_WR_CYCLE	(0x0894)
+#define AIF_MONITOR_AVR_WR_CYCLE	(0x0898)
+#define AIF_MONITOR_MIN_WRW_CYCLE	(0x089C)
+#define AIF_MONITOR_MAX_WRW_CYCLE	(0x08A0)
+#define AIF_MONITOR_AVR_WRW_CYCLE	(0x08A4)
+#define AIF_MONITOR_RBURST_CNT	(0x08A8)
+#define AIF_MONITOR_MIN_RD_CYCLE	(0x08AC)
+#define AIF_MONITOR_MAX_RD_CYCLE	(0x08B0)
+#define AIF_MONITOR_AVR_RD_CYCLE	(0x08B4)
+#define AIF_MONITOR_MIN_RDW_CYCLE	(0x08B8)
+#define AIF_MONITOR_MAX_RDW_CYCLE	(0x08BC)
+#define AIF_MONITOR_AVR_RDW_CYCLE	(0x08C0)
+#define AIF_CH_STAT_0	(0x08C4)
+#define AIF_CH_STAT_1	(0x08C8)
+
+#define AIF_MODULE_CLK_SEL	(0x0A04)
+#define AIF_MODULE_CLK_EN	(0x0A08)
+
+typedef struct dss_aif {
+	uint32_t aif_ch_ctl;
+	uint32_t aif_ch_ctl_add;
+} dss_aif_t;
+
+typedef struct dss_aif_bw {
+	uint64_t bw;
+	uint8_t chn_idx;
+	int8_t axi_sel;
+	uint8_t is_used;
+} dss_aif_bw_t;
+
+/*******************************************************************************
+ ** MIF
+ */
+#define MIF_ENABLE	(0x0000)
+#define MIF_MEM_CTRL	(0x0004)
+
+#define MIF_CTRL0	(0x000)
+#define MIF_CTRL1	(0x004)
+#define MIF_CTRL2	(0x008)
+#define MIF_CTRL3	(0x00C)
+#define MIF_CTRL4	(0x010)
+#define MIF_CTRL5	(0x014)
+#define REG_DEFAULT (0x0500)
+#define MIF_SHADOW_READ	(0x0504)
+#define MIF_CLK_CTL	(0x0508)
+
+#define MIF_STAT0	(0x0600)
+
+#define MIF_STAT1	(0x0604)
+
+#define MIF_STAT2	(0x0608)
+
+#define MIF_CTRL_OFFSET	(0x20)
+#define MIF_CH0_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*1)
+#define MIF_CH1_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*2)
+#define MIF_CH2_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*3)
+#define MIF_CH3_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*4)
+#define MIF_CH4_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*5)
+#define MIF_CH5_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*6)
+#define MIF_CH6_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*7)
+#define MIF_CH7_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*8)
+#define MIF_CH8_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*9)
+#define MIF_CH9_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*10)
+#define MIF_CH10_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*11)
+#define MIF_CH11_OFFSET	(DSS_MIF_OFFSET + MIF_CTRL_OFFSET*12)
+#define MIF_CTRL_NUM	(12)
+
+#define LITTLE_LAYER_BUF_SIZE	(256 * 1024)
+#define MIF_STRIDE_UNIT (4 * 1024)
+
+typedef struct dss_mif {
+	uint32_t mif_ctrl1;
+	uint32_t mif_ctrl2;
+	uint32_t mif_ctrl3;
+	uint32_t mif_ctrl4;
+	uint32_t mif_ctrl5;
+} dss_mif_t;
+
+/*
+ ** stretch blt, linear/tile, rotation, pixel format
+ ** 0 0 000
+ */
+enum dss_mmu_tlb_tag_org {
+	MMU_TLB_TAG_ORG_0x0 = 0x0,
+	MMU_TLB_TAG_ORG_0x1 = 0x1,
+	MMU_TLB_TAG_ORG_0x2 = 0x2,
+	MMU_TLB_TAG_ORG_0x3 = 0x3,
+	MMU_TLB_TAG_ORG_0x4 = 0x4,
+	MMU_TLB_TAG_ORG_0x7 = 0x7,
+
+	MMU_TLB_TAG_ORG_0x8 = 0x8,
+	MMU_TLB_TAG_ORG_0x9 = 0x9,
+	MMU_TLB_TAG_ORG_0xA = 0xA,
+	MMU_TLB_TAG_ORG_0xB = 0xB,
+	MMU_TLB_TAG_ORG_0xC = 0xC,
+	MMU_TLB_TAG_ORG_0xF = 0xF,
+
+	MMU_TLB_TAG_ORG_0x10 = 0x10,
+	MMU_TLB_TAG_ORG_0x11 = 0x11,
+	MMU_TLB_TAG_ORG_0x12 = 0x12,
+	MMU_TLB_TAG_ORG_0x13 = 0x13,
+	MMU_TLB_TAG_ORG_0x14 = 0x14,
+	MMU_TLB_TAG_ORG_0x17 = 0x17,
+
+	MMU_TLB_TAG_ORG_0x18 = 0x18,
+	MMU_TLB_TAG_ORG_0x19 = 0x19,
+	MMU_TLB_TAG_ORG_0x1A = 0x1A,
+	MMU_TLB_TAG_ORG_0x1B = 0x1B,
+	MMU_TLB_TAG_ORG_0x1C = 0x1C,
+	MMU_TLB_TAG_ORG_0x1F = 0x1F,
+};
+
+/*******************************************************************************
+ **SMMU
+ */
+#define SMMU_SCR	(0x0000)
+#define SMMU_MEMCTRL	(0x0004)
+#define SMMU_LP_CTRL	(0x0008)
+#define SMMU_PRESS_REMAP	(0x000C)
+#define SMMU_INTMASK_NS	(0x0010)
+#define SMMU_INTRAW_NS	(0x0014)
+#define SMMU_INTSTAT_NS	(0x0018)
+#define SMMU_INTCLR_NS	(0x001C)
+
+#define SMMU_SMRx_NS	(0x0020)
+#define SMMU_RLD_EN0_NS	(0x01F0)
+#define SMMU_RLD_EN1_NS	(0x01F4)
+#define SMMU_RLD_EN2_NS	(0x01F8)
+#define SMMU_CB_SCTRL	(0x0200)
+#define SMMU_CB_TTBR0	(0x0204)
+#define SMMU_CB_TTBR1	(0x0208)
+#define SMMU_CB_TTBCR	(0x020C)
+#define SMMU_OFFSET_ADDR_NS	(0x0210)
+#define SMMU_SCACHEI_ALL	(0x0214)
+#define SMMU_SCACHEI_L1	(0x0218)
+#define SMMU_SCACHEI_L2L3	(0x021C)
+#define SMMU_FAMA_CTRL0	(0x0220)
+#define SMMU_FAMA_CTRL1	(0x0224)
+#define SMMU_ADDR_MSB	(0x0300)
+#define SMMU_ERR_RDADDR	(0x0304)
+#define SMMU_ERR_WRADDR	(0x0308)
+#define SMMU_FAULT_ADDR_TCU (0x0310)
+#define SMMU_FAULT_ID_TCU	(0x0314)
+
+#define SMMU_FAULT_ADDR_TBUx	(0x0320)
+#define SMMU_FAULT_ID_TBUx	(0x0324)
+#define SMMU_FAULT_INFOx	(0x0328)
+#define SMMU_DBGRPTR_TLB	(0x0380)
+#define SMMU_DBGRDATA_TLB	(0x0380)
+#define SMMU_DBGRDATA0_CACHE	(0x038C)
+#define SMMU_DBGRDATA1_CACHE	(0x0390)
+#define SMMU_DBGAXI_CTRL	(0x0394)
+#define SMMU_OVA_ADDR	(0x0398)
+#define SMMU_OPA_ADDR	(0x039C)
+#define SMMU_OVA_CTRL	(0x03A0)
+#define SMMU_OPREF_ADDR	(0x03A4)
+#define SMMU_OPREF_CTRL	(0x03A8)
+#define SMMU_OPREF_CNT	(0x03AC)
+
+#define SMMU_SMRx_S	(0x0500)
+#define SMMU_RLD_EN0_S	(0x06F0)
+#define SMMU_RLD_EN1_S	(0x06F4)
+#define SMMU_RLD_EN2_S	(0x06F8)
+#define SMMU_INTMAS_S	(0x0700)
+#define SMMU_INTRAW_S	(0x0704)
+#define SMMU_INTSTAT_S	(0x0708)
+#define SMMU_INTCLR_S	(0x070C)
+#define SMMU_SCR_S	(0x0710)
+#define SMMU_SCB_SCTRL	(0x0714)
+#define SMMU_SCB_TTBR	(0x0718)
+#define SMMU_SCB_TTBCR	(0x071C)
+#define SMMU_OFFSET_ADDR_S	(0x0720)
+
+#define SMMU_SID_NUM	(64)
+
+typedef struct dss_smmu {
+	uint32_t smmu_scr;
+	uint32_t smmu_memctrl;
+	uint32_t smmu_lp_ctrl;
+	uint32_t smmu_press_remap;
+	uint32_t smmu_intmask_ns;
+	uint32_t smmu_intraw_ns;
+	uint32_t smmu_intstat_ns;
+	uint32_t smmu_intclr_ns;
+	uint32_t smmu_smrx_ns[SMMU_SID_NUM];
+	uint32_t smmu_rld_en0_ns;
+	uint32_t smmu_rld_en1_ns;
+	uint32_t smmu_rld_en2_ns;
+	uint32_t smmu_cb_sctrl;
+	uint32_t smmu_cb_ttbr0;
+	uint32_t smmu_cb_ttbr1;
+	uint32_t smmu_cb_ttbcr;
+	uint32_t smmu_offset_addr_ns;
+	uint32_t smmu_scachei_all;
+	uint32_t smmu_scachei_l1;
+	uint32_t smmu_scachei_l2l3;
+	uint32_t smmu_fama_ctrl0_ns;
+	uint32_t smmu_fama_ctrl1_ns;
+	uint32_t smmu_addr_msb;
+	uint32_t smmu_err_rdaddr;
+	uint32_t smmu_err_wraddr;
+	uint32_t smmu_fault_addr_tcu;
+	uint32_t smmu_fault_id_tcu;
+	uint32_t smmu_fault_addr_tbux;
+	uint32_t smmu_fault_id_tbux;
+	uint32_t smmu_fault_infox;
+	uint32_t smmu_dbgrptr_tlb;
+	uint32_t smmu_dbgrdata_tlb;
+	uint32_t smmu_dbgrptr_cache;
+	uint32_t smmu_dbgrdata0_cache;
+	uint32_t smmu_dbgrdata1_cache;
+	uint32_t smmu_dbgaxi_ctrl;
+	uint32_t smmu_ova_addr;
+	uint32_t smmu_opa_addr;
+	uint32_t smmu_ova_ctrl;
+	uint32_t smmu_opref_addr;
+	uint32_t smmu_opref_ctrl;
+	uint32_t smmu_opref_cnt;
+	uint32_t smmu_smrx_s[SMMU_SID_NUM];
+	uint32_t smmu_rld_en0_s;
+	uint32_t smmu_rld_en1_s;
+	uint32_t smmu_rld_en2_s;
+	uint32_t smmu_intmas_s;
+	uint32_t smmu_intraw_s;
+	uint32_t smmu_intstat_s;
+	uint32_t smmu_intclr_s;
+	uint32_t smmu_scr_s;
+	uint32_t smmu_scb_sctrl;
+	uint32_t smmu_scb_ttbr;
+	uint32_t smmu_scb_ttbcr;
+	uint32_t smmu_offset_addr_s;
+
+	uint8_t smmu_smrx_ns_used[DSS_CHN_MAX_DEFINE];
+} dss_smmu_t;
+
+/*******************************************************************************
+ ** RDMA
+ */
+
+
+#define DMA_OFT_X0	(0x0000)
+#define DMA_OFT_Y0	(0x0004)
+#define DMA_OFT_X1	(0x0008)
+#define DMA_OFT_Y1	(0x000C)
+#define DMA_MASK0	(0x0010)
+#define DMA_MASK1	(0x0014)
+#define DMA_STRETCH_SIZE_VRT	(0x0018)
+#define DMA_CTRL	(0x001C)
+#define DMA_TILE_SCRAM	(0x0020)
+
+#define DMA_PULSE	(0x0028)
+#define DMA_CORE_GT	(0x002C)
+#define RWCH_CFG0	(0x0030)
+
+
+#define WDMA_DMA_SW_MASK_EN	(0x004C)
+#define WDMA_DMA_START_MASK0	(0x0050)
+#define WDMA_DMA_END_MASK0	(0x0054)
+#define WDMA_DMA_START_MASK1	(0x0058)
+#define WDMA_DMA_END_MASK1	(0x005C)
+
+
+#define DMA_DATA_ADDR0	(0x0060)
+#define DMA_STRIDE0	(0x0064)
+#define DMA_STRETCH_STRIDE0	(0x0068)
+#define DMA_DATA_NUM0	(0x006C)
+
+#define DMA_TEST0	(0x0070)
+#define DMA_TEST1	(0x0074)
+#define DMA_TEST3	(0x0078)
+#define DMA_TEST4	(0x007C)
+#define DMA_STATUS_Y	(0x0080)
+
+
+#define DMA_DATA_ADDR1	(0x0084)
+#define DMA_STRIDE1	(0x0088)
+#define DMA_STRETCH_STRIDE1	(0x008C)
+#define DMA_DATA_NUM1	(0x0090)
+
+#define DMA_TEST0_U	(0x0094)
+#define DMA_TEST1_U	(0x0098)
+#define DMA_TEST3_U	(0x009C)
+#define DMA_TEST4_U	(0x00A0)
+#define DMA_STATUS_U	(0x00A4)
+
+
+#define DMA_DATA_ADDR2	(0x00A8)
+#define DMA_STRIDE2	(0x00AC)
+#define DMA_STRETCH_STRIDE2	(0x00B0)
+#define DMA_DATA_NUM2	(0x00B4)
+
+#define DMA_TEST0_V	(0x00B8)
+#define DMA_TEST1_V	(0x00BC)
+#define DMA_TEST3_V	(0x00C0)
+#define DMA_TEST4_V	(0x00C4)
+#define DMA_STATUS_V	(0x00C8)
+
+
+#define CH_RD_SHADOW	(0x00D0)
+#define CH_CTL	(0x00D4)
+#define CH_SECU_EN	(0x00D8)
+#define CH_SW_END_REQ	(0x00DC)
+#define CH_CLK_SEL	(0x00E0)
+#define CH_CLK_EN	(0x00E4)
+
+/*******************************************************************************
+ ** DFC
+ */
+#define DFC_DISP_SIZE	(0x0000)
+#define DFC_PIX_IN_NUM	(0x0004)
+#define DFC_GLB_ALPHA	(0x0008)
+#define DFC_DISP_FMT	(0x000C)
+#define DFC_CLIP_CTL_HRZ	(0x0010)
+#define DFC_CLIP_CTL_VRZ	(0x0014)
+#define DFC_CTL_CLIP_EN	(0x0018)
+#define DFC_ICG_MODULE	(0x001C)
+#define DFC_DITHER_ENABLE	(0x0020)
+#define DFC_PADDING_CTL	(0x0024)
+
+typedef struct dss_dfc {
+	uint32_t disp_size;
+	uint32_t pix_in_num;
+	uint32_t disp_fmt;
+	uint32_t clip_ctl_hrz;
+	uint32_t clip_ctl_vrz;
+	uint32_t ctl_clip_en;
+	uint32_t icg_module;
+	uint32_t dither_enable;
+	uint32_t padding_ctl;
+} dss_dfc_t;
+
+/*******************************************************************************
+ ** SCF
+ */
+#define DSS_SCF_H0_Y_COEF_OFFSET	(0x0000)
+#define DSS_SCF_Y_COEF_OFFSET	(0x2000)
+#define DSS_SCF_UV_COEF_OFFSET	(0x2800)
+
+#define SCF_EN_HSCL_STR	(0x0000)
+#define SCF_EN_VSCL_STR	(0x0004)
+#define SCF_H_V_ORDER	(0x0008)
+#define SCF_SCF_CORE_GT	(0x000C)
+#define SCF_INPUT_WIDTH_HEIGHT	(0x0010)
+#define SCF_OUTPUT_WIDTH_HEIGHT	(0x0014)
+#define SCF_COEF_MEM_CTRL  (0x0018)
+#define SCF_EN_HSCL	(0x001C)
+#define SCF_EN_VSCL	(0x0020)
+#define SCF_ACC_HSCL	(0x0024)
+#define SCF_ACC_HSCL1	(0x0028)
+#define SCF_INC_HSCL	(0x0034)
+#define SCF_ACC_VSCL	(0x0038)
+#define SCF_ACC_VSCL1	(0x003C)
+#define SCF_INC_VSCL	(0x0048)
+#define SCF_EN_NONLINEAR	(0x004C)
+#define SCF_EN_MMP	(0x007C)
+#define SCF_DB_H0	(0x0080)
+#define SCF_DB_H1	(0x0084)
+#define SCF_DB_V0	(0x0088)
+#define SCF_DB_V1	(0x008C)
+#define SCF_LB_MEM_CTRL	(0x0090)
+#define SCF_RD_SHADOW	(0x00F0)
+#define SCF_CLK_SEL	(0x00F8)
+#define SCF_CLK_EN	(0x00FC)
+
+/* MACROS */
+#define SCF_MIN_INPUT	(16)
+#define SCF_MIN_OUTPUT	(16)
+
+/* Threshold for SCF Stretch and SCF filter */
+#define RDMA_STRETCH_THRESHOLD	(2)
+#define SCF_INC_FACTOR	(1 << 18)
+#define SCF_UPSCALE_MAX	(60)
+#define SCF_DOWNSCALE_MAX	  (60)
+#define SCF_EDGE_FACTOR (3)
+#define ARSR2P_INC_FACTOR (65536)
+
+typedef struct dss_scl {
+	uint32_t en_hscl_str;
+	uint32_t en_vscl_str;
+	uint32_t h_v_order;
+	uint32_t input_width_height;
+	uint32_t output_width_height;
+	uint32_t en_hscl;
+	uint32_t en_vscl;
+	uint32_t acc_hscl;
+	uint32_t inc_hscl;
+	uint32_t inc_vscl;
+	uint32_t en_mmp;
+	uint32_t scf_ch_core_gt;
+	uint32_t fmt;
+} dss_scl_t;
+
+enum scl_coef_lut_idx {
+	SCL_COEF_NONE_IDX = -1,
+	SCL_COEF_YUV_IDX = 0,
+	SCL_COEF_RGB_IDX = 1,
+	SCL_COEF_IDX_MAX = 2,
+};
+
+/*******************************************************************************
+ ** ARSR2P  v0
+ */
+#define ARSR2P_INPUT_WIDTH_HEIGHT		(0x000)
+#define ARSR2P_OUTPUT_WIDTH_HEIGHT		(0x004)
+#define ARSR2P_IHLEFT		(0x008)
+#define ARSR2P_IHRIGHT		(0x00C)
+#define ARSR2P_IVTOP		(0x010)
+#define ARSR2P_IVBOTTOM		(0x014)
+#define ARSR2P_IHINC		(0x018)
+#define ARSR2P_IVINC		(0x01C)
+#define ARSR2P_UV_OFFSET		(0x020)
+#define ARSR2P_MODE		(0x024)
+#define ARSR2P_SKIN_THRES_Y		(0x028)
+#define ARSR2P_SKIN_THRES_U		(0x02C)
+#define ARSR2P_SKIN_THRES_V		(0x030)
+#define ARSR2P_SKIN_CFG0		(0x034)
+#define ARSR2P_SKIN_CFG1		(0x038)
+#define ARSR2P_SKIN_CFG2		(0x03C)
+#define ARSR2P_SHOOT_CFG1		(0x040)
+#define ARSR2P_SHOOT_CFG2		(0x044)
+#define ARSR2P_SHARP_CFG1		(0x048)
+#define ARSR2P_SHARP_CFG2		(0x04C)
+#define ARSR2P_SHARP_CFG3		(0x050)
+#define ARSR2P_SHARP_CFG4		(0x054)
+#define ARSR2P_SHARP_CFG5		(0x058)
+#define ARSR2P_SHARP_CFG6		(0x05C)
+#define ARSR2P_SHARP_CFG7		(0x060)
+#define ARSR2P_SHARP_CFG8		(0x064)
+#define ARSR2P_SHARP_CFG9		(0x068)
+#define ARSR2P_TEXTURW_ANALYSTS		(0x06C)
+#define ARSR2P_INTPLSHOOTCTRL		(0x070)
+#define ARSR2P_DEBUG0		(0x074)
+#define ARSR2P_DEBUG1		(0x078)
+#define ARSR2P_DEBUG2		(0x07C)
+#define ARSR2P_DEBUG3		(0x080)
+#define ARSR2P_LB_MEM_CTRL		(0x084)
+#define ARSR2P_IHLEFT1		(0x088)
+#define ARSR2P_IHRIGHT1		(0x090)
+#define ARSR2P_IVBOTTOM1		(0x094)
+
+#define ARSR2P_LUT_COEFY_V_OFFSET (0x0000)
+#define ARSR2P_LUT_COEFY_H_OFFSET (0x0100)
+#define ARSR2P_LUT_COEFA_V_OFFSET (0x0300)
+#define ARSR2P_LUT_COEFA_H_OFFSET (0x0400)
+#define ARSR2P_LUT_COEFUV_V_OFFSET (0x0600)
+#define ARSR2P_LUT_COEFUV_H_OFFSET (0x0700)
+
+typedef struct dss_arsr2p_effect {
+	uint32_t skin_thres_y;
+	uint32_t skin_thres_u;
+	uint32_t skin_thres_v;
+	uint32_t skin_cfg0;
+	uint32_t skin_cfg1;
+	uint32_t skin_cfg2;
+	uint32_t shoot_cfg1;
+	uint32_t shoot_cfg2;
+	uint32_t sharp_cfg1;
+	uint32_t sharp_cfg2;
+	uint32_t sharp_cfg3;
+	uint32_t sharp_cfg4;
+	uint32_t sharp_cfg5;
+	uint32_t sharp_cfg6;
+	uint32_t sharp_cfg7;
+	uint32_t sharp_cfg8;
+	uint32_t sharp_cfg9;
+	uint32_t texturw_analysts;
+	uint32_t intplshootctrl;
+} dss_arsr2p_effect_t;
+
+typedef struct dss_arsr2p {
+	uint32_t arsr_input_width_height;
+	uint32_t arsr_output_width_height;
+	uint32_t ihleft;
+	uint32_t ihright;
+	uint32_t ivtop;
+	uint32_t ivbottom;
+	uint32_t ihinc;
+	uint32_t ivinc;
+	uint32_t offset;
+	uint32_t mode;
+	dss_arsr2p_effect_t arsr2p_effect;
+	uint32_t ihleft1;
+	uint32_t ihright1;
+	uint32_t ivbottom1;
+} dss_arsr2p_t;
+
+/*******************************************************************************
+ ** POST_CLIP  v g
+ */
+#define POST_CLIP_DISP_SIZE	(0x0000)
+#define POST_CLIP_CTL_HRZ	(0x0010)
+#define POST_CLIP_CTL_VRZ	(0x0014)
+#define POST_CLIP_EN	(0x0018)
+
+typedef struct dss_post_clip {
+	uint32_t disp_size;
+	uint32_t clip_ctl_hrz;
+	uint32_t clip_ctl_vrz;
+	uint32_t ctl_clip_en;
+} dss_post_clip_t;
+
+/*******************************************************************************
+ ** PCSC v
+ */
+#define PCSC_IDC0	(0x0000)
+#define PCSC_IDC2	(0x0004)
+#define PCSC_ODC0	(0x0008)
+#define PCSC_ODC2	(0x000C)
+#define PCSC_P0	(0x0010)
+#define PCSC_P1	(0x0014)
+#define PCSC_P2	(0x0018)
+#define PCSC_P3	(0x001C)
+#define PCSC_P4	(0x0020)
+#define PCSC_ICG_MODULE	(0x0024)
+#define PCSC_MPREC	(0x0028)
+
+typedef struct dss_pcsc {
+	uint32_t pcsc_idc0;
+} dss_pcsc_t;
+
+/*******************************************************************************
+ ** CSC
+ */
+#define CSC_IDC0	(0x0000)
+#define CSC_IDC2	(0x0004)
+#define CSC_ODC0	(0x0008)
+#define CSC_ODC2	(0x000C)
+#define CSC_P0	(0x0010)
+#define CSC_P1	(0x0014)
+#define CSC_P2	(0x0018)
+#define CSC_P3	(0x001C)
+#define CSC_P4	(0x0020)
+#define CSC_ICG_MODULE	(0x0024)
+#define CSC_MPREC	(0x0028)
+
+typedef struct dss_csc {
+	uint32_t idc0;
+	uint32_t idc2;
+	uint32_t odc0;
+	uint32_t odc2;
+	uint32_t p0;
+	uint32_t p1;
+	uint32_t p2;
+	uint32_t p3;
+	uint32_t p4;
+	uint32_t icg_module;
+	uint32_t mprec;
+} dss_csc_t;
+
+/*******************************************************************************
+ **channel DEBUG
+ */
+#define CH_DEBUG_SEL (0x600)
+
+/*******************************************************************************
+ ** VPP
+ */
+#define VPP_CTRL (0x700)
+#define VPP_MEM_CTRL (0x704)
+
+/*******************************************************************************
+ **DMA BUF
+ */
+#define DMA_BUF_CTRL	(0x800)
+#define DMA_BUF_SIZE  (0x850)
+#define DMA_BUF_MEM_CTRL	(0x854)
+#define DMA_BUF_DBG0 (0x0838)
+#define DMA_BUF_DBG1 (0x083c)
+
+
+#define AFBCD_HREG_HDR_PTR_LO	(0x900)
+#define AFBCD_HREG_PIC_WIDTH	(0x904)
+#define AFBCD_HREG_PIC_HEIGHT	(0x90C)
+#define AFBCD_HREG_FORMAT	(0x910)
+#define AFBCD_CTL		(0x914)
+#define AFBCD_STR	(0x918)
+#define AFBCD_LINE_CROP	(0x91C)
+#define AFBCD_INPUT_HEADER_STRIDE	(0x920)
+#define AFBCD_PAYLOAD_STRIDE	(0x924)
+#define AFBCD_MM_BASE_0	(0x928)
+#define AFBCD_AFBCD_PAYLOAD_POINTER	(0x930)
+#define AFBCD_HEIGHT_BF_STR	(0x934)
+#define AFBCD_OS_CFG	(0x938)
+#define AFBCD_MEM_CTRL	(0x93C)
+#define AFBCD_SCRAMBLE_MODE	(0x940)
+#define AFBCD_HEADER_POINTER_OFFSET	(0x944)
+#define AFBCD_MONITOR_REG1_OFFSET	(0x948)
+#define AFBCD_MONITOR_REG2_OFFSET	(0x94C)
+#define AFBCD_MONITOR_REG3_OFFSET	(0x950)
+#define AFBCD_DEBUG_REG0_OFFSET	(0x954)
+
+
+#define AFBCE_HREG_PIC_BLKS	(0x900)
+#define AFBCE_HREG_FORMAT	(0x904)
+#define AFBCE_HREG_HDR_PTR_LO	(0x908)
+#define AFBCE_HREG_PLD_PTR_LO	(0x90C)
+#define AFBCE_PICTURE_SIZE	(0x910)
+#define AFBCE_CTL	(0x914)
+#define AFBCE_HEADER_SRTIDE	(0x918)
+#define AFBCE_PAYLOAD_STRIDE	(0x91C)
+#define AFBCE_ENC_OS_CFG	(0x920)
+#define AFBCE_MEM_CTRL	(0x924)
+#define AFBCE_QOS_CFG	(0x928)
+#define AFBCE_THRESHOLD	(0x92C)
+#define AFBCE_SCRAMBLE_MODE	(0x930)
+#define AFBCE_HEADER_POINTER_OFFSET	(0x934)
+
+
+#define ROT_FIRST_LNS	(0x530)
+#define ROT_STATE	(0x534)
+#define ROT_MEM_CTRL		(0x538)
+#define ROT_SIZE	(0x53C)
+#define ROT_CPU_CTL0	(0x540)
+#define ROT_CPU_START0	(0x544)
+#define ROT_CPU_ADDR0	(0x548)
+#define ROT_CPU_RDATA0	(0x54C)
+#define ROT_CPU_RDATA1	(0x550)
+#define ROT_CPU_WDATA0	(0x554)
+#define ROT_CPU_WDATA1	(0x558)
+#define ROT_CPU_CTL1	(0x55C)
+#define ROT_CPU_START1	(0x560)
+#define ROT_CPU_ADDR1	(0x564)
+#define ROT_CPU_RDATA2	(0x568)
+#define ROT_CPU_RDATA3	(0x56C)
+#define ROT_CPU_WDATA2	(0x570)
+#define ROT_CPU_WDATA3	(0x574)
+
+
+#define CH_REG_DEFAULT (0x0A00)
+
+/* MACROS */
+#define MIN_INTERLEAVE	(7)
+#define MAX_TILE_SURPORT_NUM	(6)
+
+/* DMA aligned limited:  128bits aligned */
+#define DMA_ALIGN_BYTES	(128 / BITS_PER_BYTE)
+#define DMA_ADDR_ALIGN	(128 / BITS_PER_BYTE)
+#define DMA_STRIDE_ALIGN	(128 / BITS_PER_BYTE)
+
+#define TILE_DMA_ADDR_ALIGN	(256 * 1024)
+
+#define DMA_IN_WIDTH_MAX	(2048)
+#define DMA_IN_HEIGHT_MAX	(8192)
+
+#define AFBC_PIC_WIDTH_MIN	(16)
+#define AFBC_PIC_WIDTH_MAX	(8192)
+#define AFBC_PIC_HEIGHT_MIN	(16)
+#define AFBC_PIC_HEIGHT_MAX	(4096)
+
+#define AFBCD_TOP_CROP_MAX	(15)
+#define AFBCD_BOTTOM_CROP_MAX	(15)
+
+
+#define AFBC_HEADER_STRIDE_BLOCK	(16)
+
+#define AFBC_PAYLOAD_STRIDE_BLOCK	(1024)
+
+#define AFBC_SUPER_GRAPH_HEADER_ADDR_ALIGN	(128)
+#define AFBC_HEADER_ADDR_ALIGN	(64)
+#define AFBC_HEADER_STRIDE_ALIGN	(64)
+
+#define AFBC_PAYLOAD_ADDR_ALIGN_32	(1024)
+#define AFBC_PAYLOAD_STRIDE_ALIGN_32	(1024)
+#define AFBC_PAYLOAD_ADDR_ALIGN_16	(512)
+#define AFBC_PAYLOAD_STRIDE_ALIGN_16	(512)
+
+
+#define AFBC_BLOCK_ALIGN	(16)
+
+#define AFBCE_IN_WIDTH_MAX	(512)
+#define WROT_IN_WIDTH_MAX	(512)
+
+#define MMBUF_BASE	(0x40)
+#define MMBUF_LINE_NUM	(8)
+#define MMBUF_ADDR_ALIGN	(64)
+
+enum DSS_AFBC_HALF_BLOCK_MODE {
+	AFBC_HALF_BLOCK_UPPER_LOWER_ALL = 0,
+	AFBC_HALF_BLOCK_LOWER_UPPER_ALL,
+	AFBC_HALF_BLOCK_UPPER_ONLY,
+	AFBC_HALF_BLOCK_LOWER_ONLY,
+};
+
+typedef struct dss_rdma {
+	uint32_t oft_x0;
+	uint32_t oft_y0;
+	uint32_t oft_x1;
+	uint32_t oft_y1;
+	uint32_t mask0;
+	uint32_t mask1;
+	uint32_t stretch_size_vrt;
+	uint32_t ctrl;
+	uint32_t tile_scram;
+
+	uint32_t data_addr0;
+	uint32_t stride0;
+	uint32_t stretch_stride0;
+	uint32_t data_num0;
+
+	uint32_t data_addr1;
+	uint32_t stride1;
+	uint32_t stretch_stride1;
+	uint32_t data_num1;
+
+	uint32_t data_addr2;
+	uint32_t stride2;
+	uint32_t stretch_stride2;
+	uint32_t data_num2;
+
+	uint32_t ch_rd_shadow;
+	uint32_t ch_ctl;
+
+	uint32_t dma_buf_ctrl;
+
+	uint32_t vpp_ctrl;
+	uint32_t vpp_mem_ctrl;
+
+	uint32_t afbcd_hreg_hdr_ptr_lo;
+	uint32_t afbcd_hreg_pic_width;
+	uint32_t afbcd_hreg_pic_height;
+	uint32_t afbcd_hreg_format;
+	uint32_t afbcd_ctl;
+	uint32_t afbcd_str;
+	uint32_t afbcd_line_crop;
+	uint32_t afbcd_input_header_stride;
+	uint32_t afbcd_payload_stride;
+	uint32_t afbcd_mm_base_0;
+
+	uint32_t afbcd_afbcd_payload_pointer;
+	uint32_t afbcd_height_bf_str;
+	uint32_t afbcd_os_cfg;
+	uint32_t afbcd_mem_ctrl;
+	uint32_t afbcd_scramble_mode;
+	uint32_t afbcd_header_pointer_offset;
+
+	uint8_t vpp_used;
+	uint8_t afbc_used;
+} dss_rdma_t;
+
+typedef struct dss_wdma {
+	uint32_t oft_x0;
+	uint32_t oft_y0;
+	uint32_t oft_x1;
+	uint32_t oft_y1;
+
+	uint32_t mask0;
+	uint32_t mask1;
+	uint32_t stretch_size_vrt;
+	uint32_t ctrl;
+	uint32_t tile_scram;
+
+	uint32_t sw_mask_en;
+	uint32_t start_mask0;
+	uint32_t end_mask0;
+	uint32_t start_mask1;
+	uint32_t end_mask1;
+
+	uint32_t data_addr;
+	uint32_t stride0;
+	uint32_t data1_addr;
+	uint32_t stride1;
+
+	uint32_t stretch_stride;
+	uint32_t data_num;
+
+	uint32_t ch_rd_shadow;
+	uint32_t ch_ctl;
+	uint32_t ch_secu_en;
+	uint32_t ch_sw_end_req;
+
+	uint32_t dma_buf_ctrl;
+	uint32_t dma_buf_size;
+
+	uint32_t rot_size;
+
+	uint32_t afbce_hreg_pic_blks;
+	uint32_t afbce_hreg_format;
+	uint32_t afbce_hreg_hdr_ptr_lo;
+	uint32_t afbce_hreg_pld_ptr_lo;
+	uint32_t afbce_picture_size;
+	uint32_t afbce_ctl;
+	uint32_t afbce_header_srtide;
+	uint32_t afbce_payload_stride;
+	uint32_t afbce_enc_os_cfg;
+	uint32_t afbce_mem_ctrl;
+	uint32_t afbce_qos_cfg;
+	uint32_t afbce_threshold;
+	uint32_t afbce_scramble_mode;
+	uint32_t afbce_header_pointer_offset;
+
+	uint8_t afbc_used;
+	uint8_t rot_used;
+} dss_wdma_t;
+
+/*******************************************************************************
+ ** CE
+
+#define CE_HIST_RESET	(0x00)
+#define CE_HIST_CTL	(0x04)
+#define CE_HIST_FRAME_CNT	(0x08)
+#define CE_SIZE	(0x0C)
+#define CE_NO_STAT_LINES	(0x10)
+#define CE_BLACK_REGION_THRE	(0x14)
+#define CE_WHITE_REGION_THRE	(0x18)
+#define CE_LUT_SEL	(0x1C)
+#define CE_LUT_ENABLE	(0x20)
+#define CE_LUT_USING_IND	(0x54)
+#define CE_STATE_IND	(0x58)
+#define CE_MEM_CTRL	(0x5C)
+
+#define CE_TOTALGRAY	(0x30)
+#define CE_TOTALPIXL	(0x34)
+#define CE_MEAN	(0x38)
+#define CE_PEC0_3	(0x3C)
+#define CE_PEC4_7	(0x40)
+#define CE_PEC8	(0x44)
+#define CE_BLACK_NUM	(0x48)
+#define CE_WHITE_NUM	(0x4C)
+#define CE_HIST_RPT_IND	(0x50)
+
+typedef struct dss_ce {
+uint32_t hist_reset;
+uint32_t hist_ctl;
+uint32_t hist_frame_cnt;
+uint32_t size;
+uint32_t no_stat_lines;
+uint32_t black_region_thre;
+uint32_t white_region_thre;
+uint32_t lut_sel;
+uint32_t lut_enable;
+uint32_t mem_ctrl;
+
+uint32_t totalgray;
+uint32_t totalpixl;
+uint32_t mean;
+uint32_t pec0_3;
+uint32_t pec4_7;
+uint32_t pec8;
+uint32_t black_num;
+uint32_t white_num;
+uint32_t hist_rpt_ind;
+char __iomem *lut_base;
+uint8_t *lut_table;
+} dss_ce_t;*/
+
+/*******************************************************************************
+ ** MCTL  MUTEX0 1 2 3 4 5
+ */
+#define MCTL_CTL_EN	(0x0000)
+#define MCTL_CTL_MUTEX	(0x0004)
+#define MCTL_CTL_MUTEX_STATUS	(0x0008)
+#define MCTL_CTL_MUTEX_ITF	(0x000C)
+#define MCTL_CTL_MUTEX_DBUF	(0x0010)
+#define MCTL_CTL_MUTEX_SCF	(0x0014)
+#define MCTL_CTL_MUTEX_OV	(0x0018)
+#define MCTL_CTL_MUTEX_WCH0	(0x0020)
+#define MCTL_CTL_MUTEX_WCH1	(0x0024)
+#define MCTL_CTL_MUTEX_WCH2	(0x0028)
+#define MCTL_CTL_MUTEX_RCH8	(0x002C)
+#define MCTL_CTL_MUTEX_RCH0	(0x0030)
+#define MCTL_CTL_MUTEX_RCH1	(0x0034)
+#define MCTL_CTL_MUTEX_RCH2	(0x0038)
+#define MCTL_CTL_MUTEX_RCH3	(0x003C)
+#define MCTL_CTL_MUTEX_RCH4	(0x0040)
+#define MCTL_CTL_MUTEX_RCH5	(0x0044)
+#define MCTL_CTL_MUTEX_RCH6	(0x0048)
+#define MCTL_CTL_MUTEX_RCH7	(0x004C)
+#define MCTL_CTL_TOP	(0x0050)
+#define MCTL_CTL_FLUSH_STATUS	(0x0054)
+#define MCTL_CTL_CLEAR	(0x0058)
+#define MCTL_CTL_CACK_TOUT	(0x0060)
+#define MCTL_CTL_MUTEX_TOUT	(0x0064)
+#define MCTL_CTL_STATUS	(0x0068)
+#define MCTL_CTL_INTEN	(0x006C)
+#define MCTL_CTL_SW_ST	(0x0070)
+#define MCTL_CTL_ST_SEL	(0x0074)
+#define MCTL_CTL_END_SEL	(0x0078)
+#define MCTL_CTL_CLK_SEL	(0x0080)
+#define MCTL_CTL_CLK_EN	(0x0084)
+#define MCTL_CTL_DBG	(0x00E0)
+
+/*******************************************************************************
+ ** MCTL  SYS
+ */
+
+#define MCTL_CTL_SECU_CFG	(0x0000)
+#define MCTL_PAY_SECU_FLUSH_EN  (0x0018)
+#define MCTL_CTL_SECU_GATE0	(0x0080)
+#define MCTL_CTL_SECU_GATE1	(0x0084)
+#define MCTL_CTL_SECU_GATE2	(0x0088)
+#define MCTL_DSI0_SECU_CFG_EN	(0x00A0)
+#define MCTL_DSI1_SECU_CFG_EN	(0x00A4)
+
+#define MCTL_RCH0_FLUSH_EN	(0x0100)
+#define MCTL_RCH1_FLUSH_EN	(0x0104)
+#define MCTL_RCH2_FLUSH_EN	(0x0108)
+#define MCTL_RCH3_FLUSH_EN	(0x010C)
+#define MCTL_RCH4_FLUSH_EN	(0x0110)
+#define MCTL_RCH5_FLUSH_EN	(0x0114)
+#define MCTL_RCH6_FLUSH_EN	(0x0118)
+#define MCTL_RCH7_FLUSH_EN	(0x011C)
+#define MCTL_WCH0_FLUSH_EN	(0x0120)
+#define MCTL_WCH1_FLUSH_EN	(0x0124)
+#define MCTL_OV0_FLUSH_EN	(0x0128)
+#define MCTL_OV1_FLUSH_EN	(0x012C)
+#define MCTL_OV2_FLUSH_EN	(0x0130)
+#define MCTL_OV3_FLUSH_EN	(0x0134)
+#define MCTL_RCH8_FLUSH_EN	(0x0138)
+#define MCTL_WCH2_FLUSH_EN	(0x013C)
+
+#define MCTL_RCH0_OV_OEN	(0x0160)
+#define MCTL_RCH1_OV_OEN	(0x0164)
+#define MCTL_RCH2_OV_OEN	(0x0168)
+#define MCTL_RCH3_OV_OEN	(0x016C)
+#define MCTL_RCH4_OV_OEN	(0x0170)
+#define MCTL_RCH5_OV_OEN	(0x0174)
+#define MCTL_RCH6_OV_OEN	(0x0178)
+#define MCTL_RCH7_OV_OEN	(0x017C)
+
+#define MCTL_RCH_OV0_SEL	(0x0180)
+#define MCTL_RCH_OV1_SEL	(0x0184)
+#define MCTL_RCH_OV2_SEL	(0x0188)
+#define MCTL_RCH_OV3_SEL	(0x018C)
+
+#define MCTL_WCH0_OV_IEN   (0x01A0)
+#define MCTL_WCH1_OV_IEN   (0x01A4)
+
+#define MCTL_WCH_OV2_SEL   (0x01A8)
+#define MCTL_WCH_OV3_SEL   (0x01AC)
+
+#define MCTL_WB_ENC_SEL	(0x01B0)
+#define MCTL_DSI_MUX_SEL	(0x01B4)
+
+#define MCTL_RCH0_STARTY	(0x01C0)
+#define MCTL_RCH1_STARTY	(0x01C4)
+#define MCTL_RCH2_STARTY	(0x01C8)
+#define MCTL_RCH3_STARTY	(0x01CC)
+#define MCTL_RCH4_STARTY	(0x01D0)
+#define MCTL_RCH5_STARTY	(0x01D4)
+#define MCTL_RCH6_STARTY	(0x01D8)
+#define MCTL_RCH7_STARTY	(0x01DC)
+
+#define MCTL_MCTL_CLK_SEL	(0x01F0)
+#define MCTL_MCTL_CLK_EN	(0x01F4)
+#define MCTL_MOD_CLK_SEL	(0x01F8)
+#define MCTL_MOD_CLK_EN	(0x01FC)
+
+#define MCTL_MOD0_DBG	(0x0200)
+#define MCTL_MOD1_DBG	(0x0204)
+#define MCTL_MOD2_DBG	(0x0208)
+#define MCTL_MOD3_DBG	(0x020C)
+#define MCTL_MOD4_DBG	(0x0210)
+#define MCTL_MOD5_DBG	(0x0214)
+#define MCTL_MOD6_DBG	(0x0218)
+#define MCTL_MOD7_DBG	(0x021C)
+#define MCTL_MOD8_DBG	(0x0220)
+#define MCTL_MOD9_DBG	(0x0224)
+#define MCTL_MOD10_DBG	(0x0228)
+#define MCTL_MOD11_DBG	(0x022C)
+#define MCTL_MOD12_DBG	(0x0230)
+#define MCTL_MOD13_DBG	(0x0234)
+#define MCTL_MOD14_DBG	(0x0238)
+#define MCTL_MOD15_DBG	(0x023C)
+#define MCTL_MOD16_DBG	(0x0240)
+#define MCTL_MOD17_DBG	(0x0244)
+#define MCTL_MOD18_DBG	(0x0248)
+#define MCTL_MOD19_DBG	(0x024C)
+#define MCTL_MOD20_DBG	(0x0250)
+#define MCTL_MOD0_STATUS	(0x0280)
+#define MCTL_MOD1_STATUS	(0x0284)
+#define MCTL_MOD2_STATUS	(0x0288)
+#define MCTL_MOD3_STATUS	(0x028C)
+#define MCTL_MOD4_STATUS	(0x0290)
+#define MCTL_MOD5_STATUS	(0x0294)
+#define MCTL_MOD6_STATUS	(0x0298)
+#define MCTL_MOD7_STATUS	(0x029C)
+#define MCTL_MOD8_STATUS	(0x02A0)
+#define MCTL_MOD9_STATUS	(0x02A4)
+#define MCTL_MOD10_STATUS	(0x02A8)
+#define MCTL_MOD11_STATUS	(0x02AC)
+#define MCTL_MOD12_STATUS	(0x02B0)
+#define MCTL_MOD13_STATUS	(0x02B4)
+#define MCTL_MOD14_STATUS	(0x02B8)
+#define MCTL_MOD15_STATUS	(0x02BC)
+#define MCTL_MOD16_STATUS	(0x02C0)
+#define MCTL_MOD17_STATUS	(0x02C4)
+#define MCTL_MOD18_STATUS	(0x02C8)
+#define MCTL_MOD19_STATUS	(0x02CC)
+#define MCTL_MOD20_STATUS	(0x02D0)
+#define MCTL_SW_DBG	(0x0300)
+#define MCTL_SW0_STATUS0	(0x0304)
+#define MCTL_SW0_STATUS1	(0x0308)
+#define MCTL_SW0_STATUS2	(0x030C)
+#define MCTL_SW0_STATUS3	(0x0310)
+#define MCTL_SW0_STATUS4	(0x0314)
+#define MCTL_SW0_STATUS5	(0x0318)
+#define MCTL_SW0_STATUS6	(0x031C)
+#define MCTL_SW0_STATUS7	(0x0320)
+#define MCTL_SW1_STATUS	(0x0324)
+
+
+#define MCTL_MOD_DBG_CH_NUM (10)
+#define MCTL_MOD_DBG_OV_NUM (4)
+#define MCTL_MOD_DBG_DBUF_NUM (2)
+#define MCTL_MOD_DBG_SCF_NUM (1)
+#define MCTL_MOD_DBG_ITF_NUM (2)
+#define MCTL_MOD_DBG_ADD_CH_NUM (2)
+
+enum dss_mctl_idx {
+	DSS_MCTL0 = 0,
+	DSS_MCTL1,
+	DSS_MCTL2,
+	DSS_MCTL3,
+	DSS_MCTL4,
+	DSS_MCTL5,
+	DSS_MCTL_IDX_MAX,
+};
+
+typedef struct dss_mctl {
+	uint32_t ctl_mutex_itf;
+	uint32_t ctl_mutex_dbuf;
+	uint32_t ctl_mutex_scf;
+	uint32_t ctl_mutex_ov;
+} dss_mctl_t;
+
+typedef struct dss_mctl_ch_base {
+	char __iomem *chn_mutex_base;
+	char __iomem *chn_flush_en_base;
+	char __iomem *chn_ov_en_base;
+	char __iomem *chn_starty_base;
+	char __iomem *chn_mod_dbg_base;
+} dss_mctl_ch_base_t;
+
+typedef struct dss_mctl_ch {
+	uint32_t chn_mutex;
+	uint32_t chn_flush_en;
+	uint32_t chn_ov_oen;
+	uint32_t chn_starty;
+	uint32_t chn_mod_dbg;
+} dss_mctl_ch_t;
+
+typedef struct dss_mctl_sys {
+	uint32_t ov_flush_en[DSS_OVL_IDX_MAX];
+	uint32_t chn_ov_sel[DSS_OVL_IDX_MAX];
+	uint32_t wchn_ov_sel[DSS_WCH_MAX];
+	uint8_t ov_flush_en_used[DSS_OVL_IDX_MAX];
+	uint8_t chn_ov_sel_used[DSS_OVL_IDX_MAX];
+	uint8_t wch_ov_sel_used[DSS_WCH_MAX];
+} dss_mctl_sys_t;
+
+/*******************************************************************************
+ ** OVL
+ */
+#define OVL_SIZE	(0x0000)
+#define OVL_BG_COLOR	(0x4)
+#define OVL_DST_STARTPOS	(0x8)
+#define OVL_DST_ENDPOS	(0xC)
+#define OVL_GCFG	(0x10)
+#define OVL_LAYER0_POS	(0x14)
+#define OVL_LAYER0_SIZE	(0x18)
+#define OVL_LAYER0_SRCLOKEY	(0x1C)
+#define OVL_LAYER0_SRCHIKEY	(0x20)
+#define OVL_LAYER0_DSTLOKEY	(0x24)
+#define OVL_LAYER0_DSTHIKEY	(0x28)
+#define OVL_LAYER0_PATTERN	(0x2C)
+#define OVL_LAYER0_ALPHA	(0x30)
+#define OVL_LAYER0_CFG	(0x34)
+#define OVL_LAYER0_INFO_ALPHA	(0x40)
+#define OVL_LAYER0_INFO_SRCCOLOR	(0x44)
+#define OVL_LAYER1_POS	(0x50)
+#define OVL_LAYER1_SIZE	(0x54)
+#define OVL_LAYER1_SRCLOKEY	(0x58)
+#define OVL_LAYER1_SRCHIKEY	(0x5C)
+#define OVL_LAYER1_DSTLOKEY	(0x60)
+#define OVL_LAYER1_DSTHIKEY	(0x64)
+#define OVL_LAYER1_PATTERN	(0x68)
+#define OVL_LAYER1_ALPHA	(0x6C)
+#define OVL_LAYER1_CFG	(0x70)
+#define OVL_LAYER1_INFO_ALPHA	(0x7C)
+#define OVL_LAYER1_INFO_SRCCOLOR	(0x80)
+#define OVL_LAYER2_POS	(0x8C)
+#define OVL_LAYER2_SIZE	(0x90)
+#define OVL_LAYER2_SRCLOKEY	(0x94)
+#define OVL_LAYER2_SRCHIKEY	(0x98)
+#define OVL_LAYER2_DSTLOKEY	(0x9C)
+#define OVL_LAYER2_DSTHIKEY	(0xA0)
+#define OVL_LAYER2_PATTERN	(0xA4)
+#define OVL_LAYER2_ALPHA	(0xA8)
+#define OVL_LAYER2_CFG	(0xAC)
+#define OVL_LAYER2_INFO_ALPHA	(0xB8)
+#define OVL_LAYER2_INFO_SRCCOLOR	(0xBC)
+#define OVL_LAYER3_POS	(0xC8)
+#define OVL_LAYER3_SIZE	(0xCC)
+#define OVL_LAYER3_SRCLOKEY	(0xD0)
+#define OVL_LAYER3_SRCHIKEY	(0xD4)
+#define OVL_LAYER3_DSTLOKEY	(0xD8)
+#define OVL_LAYER3_DSTHIKEY	(0xDC)
+#define OVL_LAYER3_PATTERN	(0xE0)
+#define OVL_LAYER3_ALPHA	(0xE4)
+#define OVL_LAYER3_CFG	(0xE8)
+#define OVL_LAYER3_INFO_ALPHA	(0xF4)
+#define OVL_LAYER3_INFO_SRCCOLOR	(0xF8)
+#define OVL_LAYER4_POS	(0x104)
+#define OVL_LAYER4_SIZE	(0x108)
+#define OVL_LAYER4_SRCLOKEY	(0x10C)
+#define OVL_LAYER4_SRCHIKEY	(0x110)
+#define OVL_LAYER4_DSTLOKEY	(0x114)
+#define OVL_LAYER4_DSTHIKEY	(0x118)
+#define OVL_LAYER4_PATTERN	(0x11C)
+#define OVL_LAYER4_ALPHA	(0x120)
+#define OVL_LAYER4_CFG	(0x124)
+#define OVL_LAYER4_INFO_ALPHA	(0x130)
+#define OVL_LAYER4_INFO_SRCCOLOR	(0x134)
+#define OVL_LAYER5_POS	(0x140)
+#define OVL_LAYER5_SIZE	(0x144)
+#define OVL_LAYER5_SRCLOKEY	(0x148)
+#define OVL_LAYER5_SRCHIKEY	(0x14C)
+#define OVL_LAYER5_DSTLOKEY	(0x150)
+#define OVL_LAYER5_DSTHIKEY	(0x154)
+#define OVL_LAYER5_PATTERN	(0x158)
+#define OVL_LAYER5_ALPHA	(0x15C)
+#define OVL_LAYER5_CFG	(0x160)
+#define OVL_LAYER5_INFO_ALPHA	(0x16C)
+#define OVL_LAYER5_INFO_SRCCOLOR	(0x170)
+#define OVL_LAYER6_POS	(0x14)
+#define OVL_LAYER6_SIZE	(0x18)
+#define OVL_LAYER6_SRCLOKEY	(0x1C)
+#define OVL_LAYER6_SRCHIKEY	(0x20)
+#define OVL_LAYER6_DSTLOKEY	(0x24)
+#define OVL_LAYER6_DSTHIKEY	(0x28)
+#define OVL_LAYER6_PATTERN	(0x2C)
+#define OVL_LAYER6_ALPHA	(0x30)
+#define OVL_LAYER6_CFG	(0x34)
+#define OVL_LAYER6_INFO_ALPHA	(0x40)
+#define OVL_LAYER6_INFO_SRCCOLOR	(0x44)
+#define OVL_LAYER7_POS	(0x50)
+#define OVL_LAYER7_SIZE	(0x54)
+#define OVL_LAYER7_SRCLOKEY	(0x58)
+#define OVL_LAYER7_SRCHIKEY	(0x5C)
+#define OVL_LAYER7_DSTLOKEY	(0x60)
+#define OVL_LAYER7_DSTHIKEY	(0x64)
+#define OVL_LAYER7_PATTERN	(0x68)
+#define OVL_LAYER7_ALPHA	(0x6C)
+#define OVL_LAYER7_CFG	(0x70)
+#define OVL_LAYER7_INFO_ALPHA	(0x7C)
+#define OVL_LAYER7_INFO_SRCCOLOR	(0x80)
+#define OVL_LAYER0_ST_INFO	(0x48)
+#define OVL_LAYER1_ST_INFO	(0x84)
+#define OVL_LAYER2_ST_INFO	(0xC0)
+#define OVL_LAYER3_ST_INFO	(0xFC)
+#define OVL_LAYER4_ST_INFO	(0x138)
+#define OVL_LAYER5_ST_INFO	(0x174)
+#define OVL_LAYER6_ST_INFO	(0x48)
+#define OVL_LAYER7_ST_INFO	(0x84)
+#define OVL_LAYER0_IST_INFO	(0x4C)
+#define OVL_LAYER1_IST_INFO	(0x88)
+#define OVL_LAYER2_IST_INFO	(0xC4)
+#define OVL_LAYER3_IST_INFO	(0x100)
+#define OVL_LAYER4_IST_INFO	(0x13C)
+#define OVL_LAYER5_IST_INFO	(0x178)
+#define OVL_LAYER6_IST_INFO	(0x4C)
+#define OVL_LAYER7_IST_INFO	(0x88)
+#define OVL_LAYER0_PSPOS	(0x38)
+#define OVL_LAYER0_PEPOS	(0x3C)
+#define OVL_LAYER1_PSPOS	(0x74)
+#define OVL_LAYER1_PEPOS	(0x78)
+#define OVL_LAYER2_PSPOS	(0xB0)
+#define OVL_LAYER2_PEPOS	(0xB4)
+#define OVL_LAYER3_PSPOS	(0xEC)
+#define OVL_LAYER3_PEPOS	(0xF0)
+#define OVL_LAYER4_PSPOS	(0x128)
+#define OVL_LAYER4_PEPOS	(0x12C)
+#define OVL_LAYER5_PSPOS	(0x164)
+#define OVL_LAYER5_PEPOS	(0x168)
+#define OVL_LAYER6_PSPOS	(0x38)
+#define OVL_LAYER6_PEPOS	(0x3C)
+#define OVL_LAYER7_PSPOS	(0x74)
+#define OVL_LAYER7_PEPOS	(0x78)
+
+#define OVL6_BASE_ST_INFO	(0x17C)
+#define OVL6_BASE_IST_INFO	(0x180)
+#define OVL6_GATE_CTRL	(0x184)
+#define OVL6_RD_SHADOW_SEL	(0x188)
+#define OVL6_OV_CLK_SEL	(0x18C)
+#define OVL6_OV_CLK_EN	(0x190)
+#define OVL6_BLOCK_SIZE	(0x1A0)
+#define OVL6_BLOCK_DBG	(0x1A4)
+#define OVL6_REG_DEFAULT (0x1A8)
+
+#define OVL2_BASE_ST_INFO	(0x8C)
+#define OVL2_BASE_IST_INFO	(0x90)
+#define OVL2_GATE_CTRL	(0x94)
+#define OVL2_OV_RD_SHADOW_SEL	(0x98)
+#define OVL2_OV_CLK_SEL	(0x9C)
+#define OVL2_OV_CLK_EN	(0xA0)
+#define OVL2_BLOCK_SIZE	(0xB0)
+#define OVL2_BLOCK_DBG	(0xB4)
+#define OVL2_REG_DEFAULT	(0xB8)
+
+/* LAYER0_CFG */
+#define BIT_OVL_LAYER_SRC_CFG	BIT(8)
+#define BIT_OVL_LAYER_ENABLE	BIT(0)
+
+/* LAYER0_INFO_ALPHA */
+#define BIT_OVL_LAYER_SRCALPHA_FLAG	BIT(3)
+#define BIT_OVL_LAYER_DSTALPHA_FLAG	BIT(2)
+
+/* LAYER0_INFO_SRCCOLOR */
+#define BIT_OVL_LAYER_SRCCOLOR_FLAG	BIT(0)
+
+#define OVL_6LAYER_NUM		(6)
+#define OVL_2LAYER_NUM		(2)
+
+typedef struct dss_ovl_layer {
+	uint32_t layer_pos;
+	uint32_t layer_size;
+	uint32_t layer_pattern;
+	uint32_t layer_alpha;
+	uint32_t layer_cfg;
+
+} dss_ovl_layer_t;
+
+typedef struct dss_ovl_layer_pos {
+	uint32_t layer_pspos;
+	uint32_t layer_pepos;
+
+} dss_ovl_layer_pos_t;
+
+typedef struct dss_ovl {
+	uint32_t ovl_size;
+	uint32_t ovl_bg_color;
+	uint32_t ovl_dst_startpos;
+	uint32_t ovl_dst_endpos;
+	uint32_t ovl_gcfg;
+	uint32_t ovl_block_size;
+	dss_ovl_layer_t ovl_layer[OVL_6LAYER_NUM];
+	dss_ovl_layer_pos_t ovl_layer_pos[OVL_6LAYER_NUM];
+	uint8_t ovl_layer_used[OVL_6LAYER_NUM];
+} dss_ovl_t;
+
+typedef struct dss_ovl_alpha {
+	uint32_t src_amode;
+	uint32_t src_gmode;
+	uint32_t alpha_offsrc;
+	uint32_t src_lmode;
+	uint32_t src_pmode;
+
+	uint32_t alpha_smode;
+
+	uint32_t dst_amode;
+	uint32_t dst_gmode;
+	uint32_t alpha_offdst;
+	uint32_t dst_pmode;
+
+	uint32_t fix_mode;
+} dss_ovl_alpha_t;
+
+/*******************************************************************************
+ ** DBUF
+ */
+#define DBUF_FRM_SIZE	(0x0000)
+#define DBUF_FRM_HSIZE	(0x0004)
+#define DBUF_SRAM_VALID_NUM	(0x0008)
+#define DBUF_WBE_EN	(0x000C)
+#define DBUF_THD_FILL_LEV0	(0x0010)
+#define DBUF_DFS_FILL_LEV1	(0x0014)
+#define DBUF_THD_RQOS	(0x0018)
+#define DBUF_THD_WQOS	(0x001C)
+#define DBUF_THD_CG	(0x0020)
+#define DBUF_THD_OTHER	(0x0024)
+#define DBUF_FILL_LEV0_CNT	(0x0028)
+#define DBUF_FILL_LEV1_CNT	(0x002C)
+#define DBUF_FILL_LEV2_CNT	(0x0030)
+#define DBUF_FILL_LEV3_CNT	(0x0034)
+#define DBUF_FILL_LEV4_CNT	(0x0038)
+#define DBUF_ONLINE_FILL_LEVEL	(0x003C)
+#define DBUF_WB_FILL_LEVEL	(0x0040)
+#define DBUF_DFS_STATUS	(0x0044)
+#define DBUF_THD_FLUX_REQ_BEF	(0x0048)
+#define DBUF_DFS_LP_CTRL	(0x004C)
+#define DBUF_RD_SHADOW_SEL	(0x0050)
+#define DBUF_MEM_CTRL	(0x0054)
+#define DBUF_PM_CTRL	(0x0058)
+#define DBUF_CLK_SEL	(0x005C)
+#define DBUF_CLK_EN  	(0x0060)
+#define DBUF_THD_FLUX_REQ_AFT (0x0064)
+#define DBUF_THD_DFS_OK (0x0068)
+#define DBUF_FLUX_REQ_CTRL (0x006C)
+#define DBUF_REG_DEFAULT  (0x00A4)
+
+/*******************************************************************************
+ ** SBL
+ */
+
+#define SBL_REG_FRMT_MODE                                (0x0000)
+#define SBL_REG_FRMT_DBUF_CTRL                           (0x0008)
+#define SBL_REG_FRMT_FRAME_WIDTH_7_TO_0                  (0x0010)
+#define SBL_REG_FRMT_FRAME_WIDTH_15_TO_8                 (0x0014)
+#define SBL_REG_FRMT_FRAME_HEIGHT_7_TO_0                 (0x0018)
+#define SBL_REG_FRMT_FRAME_HEIGHT_15_TO_8                (0x001c)
+#define SBL_REG_FRMT_ROI_HOR_START_7_TO_0                (0x0080)
+#define SBL_REG_FRMT_ROI_HOR_START_15_TO_8               (0x0084)
+#define SBL_REG_FRMT_ROI_HOR_END_7_TO_0                  (0x0088)
+#define SBL_REG_FRMT_ROI_HOR_END_15_TO_8                 (0x008c)
+#define SBL_REG_FRMT_ROI_VER_START_7_TO_0                (0x0090)
+#define SBL_REG_FRMT_ROI_VER_START_15_TO_8               (0x0094)
+#define SBL_REG_FRMT_ROI_VER_END_7_TO_0                  (0x0098)
+#define SBL_REG_FRMT_ROI_VER_END_15_TO_8                 (0x009c)
+#define SBL_REG_CALC_CONTROL_0                           (0x0400)
+#define SBL_REG_CALC_CONTROL_1                           (0x0404)
+#define SBL_REG_CALC_AMBIENT_LIGHT_7_TO_0                (0x0408)
+#define SBL_REG_CALC_AMBIENT_LIGHT_15_TO_8               (0x040c)
+#define SBL_REG_CALC_BACKLIGHT_7_TO_0                    (0x0410)
+#define SBL_REG_CALC_BACKLIGHT_15_TO_8                   (0x0414)
+#define SBL_REG_CALC_ASSERTIVENESS                       (0x0418)
+#define SBL_REG_CALC_TF_CONTROL                          (0x041c)
+#define SBL_REG_CALC_STRENGTH_MANUAL_7_TO_0              (0x0420)
+#define SBL_REG_CALC_STRENGTH_MANUAL_9_TO_8              (0x0424)
+#define SBL_REG_CALC_GAIN_AA_MANUAL_7_TO_0               (0x0428)
+#define SBL_REG_CALC_GAIN_AA_MANUAL_11_TO_8              (0x042c)
+#define SBL_REG_CALC_ROI_FACTOR_IN_7_TO_0                (0x0430)
+#define SBL_REG_CALC_ROI_FACTOR_IN_15_TO_8               (0x0434)
+#define SBL_REG_CALC_ROI_FACTOR_OUT_7_TO_0               (0x0438)
+#define SBL_REG_CALC_ROI_FACTOR_OUT_15_TO_8              (0x043c)
+#define SBL_REG_CALC_PSR_DELTA_CHANGE_7_TO_0             (0x0448)
+#define SBL_REG_CALC_PSR_DELTA_CHANGE_15_TO_8            (0x044c)
+#define SBL_REG_CALC_PSR_DELTA_SETTLE_7_TO_0             (0x0450)
+#define SBL_REG_CALC_PSR_DELTA_SETTLE_15_TO_8            (0x0454)
+#define SBL_REG_CALC_AL_SCALE_7_TO_0                     (0x0458)
+#define SBL_REG_CALC_AL_SCALE_15_TO_8                    (0x045c)
+#define SBL_REG_CALC_AL_TF_STEP_SAMPLE                   (0x0460)
+#define SBL_REG_CALC_AL_TF_STEP_WAIT_7_TO_0              (0x0468)
+#define SBL_REG_CALC_AL_TF_STEP_WAIT_11_TO_8             (0x046c)
+#define SBL_REG_CALC_AL_TF_STEP_WAITUP_7_TO_0            (0x0470)
+#define SBL_REG_CALC_AL_TF_STEP_WAITUP_11_TO_8           (0x0474)
+#define SBL_REG_CALC_AL_TF_STEP_SIZE_7_TO_0              (0x0478)
+#define SBL_REG_CALC_AL_TF_STEP_SIZE_11_TO_8             (0x047c)
+#define SBL_REG_CALC_AL_TF_LIMIT_7_TO_0                  (0x0480)
+#define SBL_REG_CALC_AL_TF_LIMIT_15_TO_8                 (0x0484)
+#define SBL_REG_CALC_AL_TF_ALPHA                         (0x0488)
+#define SBL_REG_CALC_AL_TF_ALPHA_UP                      (0x048c)
+#define SBL_REG_CALC_AL_TF_NOISE_7_TO_0                  (0x0490)
+#define SBL_REG_CALC_AL_TF_NOISE_15_TO_8                 (0x0494)
+#define SBL_REG_CALC_AL_TF_M_INC_7_TO_0                  (0x0498)
+#define SBL_REG_CALC_AL_TF_M_INC_15_TO_8                 (0x049c)
+#define SBL_REG_CALC_AL_TF_K_INC_7_TO_0                  (0x04a0)
+#define SBL_REG_CALC_AL_TF_K_INC_15_TO_8                 (0x04a4)
+#define SBL_REG_CALC_AL_TF_M_DEC_7_TO_0                  (0x04a8)
+#define SBL_REG_CALC_AL_TF_M_DEC_15_TO_8                 (0x04ac)
+#define SBL_REG_CALC_AL_TF_K_DEC_7_TO_0                  (0x04b0)
+#define SBL_REG_CALC_AL_TF_K_DEC_15_TO_8                 (0x04b4)
+#define SBL_REG_CALC_AL_TF_AGGRESSIVENESS                (0x04b8)
+#define SBL_REG_CALC_AL_RTF_FILTER_A_7_TO_0              (0x04c0)
+#define SBL_REG_CALC_AL_RTF_FILTER_A_15_TO_8             (0x04c4)
+#define SBL_REG_CALC_AL_RTF_FILTER_B_7_TO_0              (0x04c8)
+#define SBL_REG_CALC_AL_RTF_FILTER_B_15_TO_8             (0x04cc)
+#define SBL_REG_CALC_AL_RTF_FILTER_C_7_TO_0              (0x04d0)
+#define SBL_REG_CALC_AL_RTF_FILTER_C_15_TO_8             (0x04d4)
+#define SBL_REG_CALC_AB_AL_KNEE1_7_TO_0                  (0x04d8)
+#define SBL_REG_CALC_AB_AL_KNEE1_15_TO_8                 (0x04dc)
+#define SBL_REG_CALC_AB_AL_KNEE2_7_TO_0                  (0x04e0)
+#define SBL_REG_CALC_AB_AL_KNEE2_15_TO_8                 (0x04e4)
+#define SBL_REG_CALC_AB_BL_KNEE1_7_TO_0                  (0x04e8)
+#define SBL_REG_CALC_AB_BL_KNEE1_15_TO_8                 (0x04ec)
+#define SBL_REG_CALC_AB_BL_KNEE2_7_TO_0                  (0x04f0)
+#define SBL_REG_CALC_AB_BL_KNEE2_15_TO_8                 (0x04f4)
+#define SBL_REG_CALC_BL_PANEL_MAX_7_TO_0                 (0x04f8)
+#define SBL_REG_CALC_BL_PANEL_MAX_15_TO_8                (0x04fc)
+#define SBL_REG_CALC_BL_OFFSET_7_TO_0                    (0x0500)
+#define SBL_REG_CALC_BL_OFFSET_15_TO_8                   (0x0504)
+#define SBL_REG_CALC_BL_MIN_7_TO_0                       (0x0508)
+#define SBL_REG_CALC_BL_MIN_15_TO_8                      (0x050c)
+#define SBL_REG_CALC_BL_ATTEN_ALPHA_7_TO_0               (0x0510)
+#define SBL_REG_CALC_BL_ATTEN_ALPHA_9_TO_8               (0x0514)
+#define SBL_REG_CALC_SBC1_TF_DEPTH_7_TO_0                (0x0518)
+#define SBL_REG_CALC_SBC1_TF_DEPTH_15_TO_8               (0x051c)
+#define SBL_REG_CALC_SBC1_TF_STEP_7_TO_0                 (0x0520)
+#define SBL_REG_CALC_SBC1_TF_STEP_15_TO_8                (0x0524)
+#define SBL_REG_CALC_SBC1_TF_ASYM                        (0x0528)
+#define SBL_REG_CALC_SBC1_TF_DEPTH_LOG_7_TO_0            (0x0530)
+#define SBL_REG_CALC_SBC1_TF_DEPTH_LOG_15_TO_8           (0x0534)
+#define SBL_REG_CALC_SBC1_TF_STEP_LOG_7_TO_0             (0x0538)
+#define SBL_REG_CALC_SBC1_TF_STEP_LOG_15_TO_8            (0x053c)
+#define SBL_REG_CALC_SBC1_TF_ASYM_LOG                    (0x0540)
+#define SBL_REG_CALC_SBC2_TF_DEPTH_7_TO_0                (0x0548)
+#define SBL_REG_CALC_SBC2_TF_DEPTH_15_TO_8               (0x054c)
+#define SBL_REG_CALC_SBC2_TF_STEP_7_TO_0                 (0x0550)
+#define SBL_REG_CALC_SBC2_TF_STEP_15_TO_8                (0x0554)
+#define SBL_REG_CALC_SBC2_TF_ASYM                        (0x0558)
+#define SBL_REG_CALC_SBC2_TF_DEPTH_LOG_7_TO_0            (0x0560)
+#define SBL_REG_CALC_SBC2_TF_DEPTH_LOG_15_TO_8           (0x0564)
+#define SBL_REG_CALC_SBC2_TF_STEP_LOG_7_TO_0             (0x0568)
+#define SBL_REG_CALC_SBC2_TF_STEP_LOG_15_TO_8            (0x056c)
+#define SBL_REG_CALC_SBC2_TF_ASYM_LOG                    (0x0570)
+#define SBL_REG_CALC_CALIBRATION_A_7_TO_0                (0x05b8)
+#define SBL_REG_CALC_CALIBRATION_A_15_TO_8               (0x05bc)
+#define SBL_REG_CALC_CALIBRATION_B_7_TO_0                (0x05c0)
+#define SBL_REG_CALC_CALIBRATION_B_15_TO_8               (0x05c4)
+#define SBL_REG_CALC_CALIBRATION_C_7_TO_0                (0x05c8)
+#define SBL_REG_CALC_CALIBRATION_C_15_TO_8               (0x05cc)
+#define SBL_REG_CALC_CALIBRATION_D_7_TO_0                (0x05d0)
+#define SBL_REG_CALC_CALIBRATION_D_15_TO_8               (0x05d4)
+#define SBL_REG_CALC_CALIBRATION_E_7_TO_0                (0x05d8)
+#define SBL_REG_CALC_CALIBRATION_E_15_TO_8               (0x05dc)
+#define SBL_REG_CALC_BACKLIGHT_SCALE_7_TO_0              (0x05e0)
+#define SBL_REG_CALC_BACKLIGHT_SCALE_15_TO_8             (0x05e4)
+#define SBL_REG_CALC_GAIN_AA_TF_DEPTH_7_TO_0             (0x05e8)
+#define SBL_REG_CALC_GAIN_AA_TF_DEPTH_15_TO_8            (0x05ec)
+#define SBL_REG_CALC_GAIN_AA_TF_STEP_7_TO_0              (0x05f0)
+#define SBL_REG_CALC_GAIN_AA_TF_STEP_11_TO_8             (0x05f4)
+#define SBL_REG_CALC_GAIN_AA_TF_ASYM                     (0x05f8)
+#define SBL_REG_CALC_STRENGTH_LIMIT_7_TO_0               (0x0600)
+#define SBL_REG_CALC_STRENGTH_LIMIT_9_TO_8               (0x0604)
+#define SBL_REG_CALC_ICUT_HIST_MIN                       (0x0608)
+#define SBL_REG_CALC_ICUT_BL_MIN_7_TO_0                  (0x0610)
+#define SBL_REG_CALC_ICUT_BL_MIN_15_TO_8                 (0x0614)
+#define SBL_REG_CALC_GAIN_CA_TF_DEPTH_7_TO_0             (0x0618)
+#define SBL_REG_CALC_GAIN_CA_TF_DEPTH_15_TO_8            (0x061c)
+#define SBL_REG_CALC_GAIN_CA_TF_STEP_7_TO_0              (0x0620)
+#define SBL_REG_CALC_GAIN_CA_TF_STEP_11_TO_8             (0x0624)
+#define SBL_REG_CALC_GAIN_CA_TF_ASYM                     (0x0628)
+#define SBL_REG_CALC_GAIN_MAX_7_TO_0                     (0x0630)
+#define SBL_REG_CALC_GAIN_MAX_11_TO_8                    (0x0634)
+#define SBL_REG_CALC_GAIN_MIDDLE_7_TO_0                  (0x0638)
+#define SBL_REG_CALC_GAIN_MIDDLE_11_TO_8                 (0x063c)
+#define SBL_REG_CALC_BRIGHTPR                            (0x0640)
+#define SBL_REG_CALC_BPR_CORRECT                         (0x0648)
+#define SBL_CALC_BACKLIGHT_OUT_7_TO_0                    (0x0650)
+#define SBL_CALC_BACKLIGHT_OUT_15_TO_8                   (0x0654)
+#define SBL_CALC_STRENGTH_INROI_OUT_7_TO_0               (0x0658)
+#define SBL_CALC_STRENGTH_INROI_OUT_9_TO_8               (0x065c)
+#define SBL_CALC_STRENGTH_OUTROI_OUT_7_TO_0              (0x0660)
+#define SBL_CALC_STRENGTH_OUTROI_OUT_9_TO_8              (0x0664)
+#define SBL_CALC_DARKENH_OUT_7_TO_0                      (0x0668)
+#define SBL_CALC_DARKENH_OUT_15_TO_8                     (0x066c)
+#define SBL_CALC_BRIGHTPR_OUT                            (0x0670)
+#define SBL_CALC_STAT_OUT_7_TO_0                         (0x0678)
+#define SBL_CALC_STAT_OUT_15_TO_8                        (0x067c)
+#define SBL_REG_CALC_AL_DELTA_SETTLE_7_TO_0              (0x0680)
+#define SBL_REG_CALC_AL_DELTA_SETTLE_15_TO_8             (0x0684)
+#define SBL_REG_CALC_BL_DELTA_SETTLE_7_TO_0              (0x0688)
+#define SBL_REG_CALC_BL_DELTA_SETTLE_15_TO_8             (0x068c)
+#define SBL_CALC_AL_CALIB_LUT_ADDR_I                     (0x06c0)
+#define SBL_CALC_AL_CALIB_LUT_DATA_W_7_TO_0              (0x06d0)
+#define SBL_CALC_AL_CALIB_LUT_DATA_W_15_TO_8             (0x06d4)
+#define SBL_CALC_BL_IN_LUT_ADDR_I                        (0x0700)
+#define SBL_CALC_BL_IN_LUT_DATA_W_7_TO_0                 (0x0710)
+#define SBL_CALC_BL_IN_LUT_DATA_W_15_TO_8                (0x0714)
+#define SBL_CALC_BL_OUT_LUT_ADDR_I                       (0x0740)
+#define SBL_CALC_BL_OUT_LUT_DATA_W_7_TO_0                (0x0750)
+#define SBL_CALC_BL_OUT_LUT_DATA_W_15_TO_8               (0x0754)
+#define SBL_CALC_BL_ATTEN_LUT_ADDR_I                     (0x0780)
+#define SBL_CALC_BL_ATTEN_LUT_DATA_W_7_TO_0              (0x0790)
+#define SBL_CALC_BL_ATTEN_LUT_DATA_W_15_TO_8             (0x0794)
+#define SBL_CALC_BL_AUTO_LUT_ADDR_I                      (0x07c0)
+#define SBL_CALC_BL_AUTO_LUT_DATA_W_7_TO_0               (0x07d0)
+#define SBL_CALC_BL_AUTO_LUT_DATA_W_15_TO_8              (0x07d4)
+#define SBL_CALC_AL_CHANGE_LUT_ADDR_I                    (0x0800)
+#define SBL_CALC_AL_CHANGE_LUT_DATA_W_7_TO_0             (0x0810)
+#define SBL_CALC_AL_CHANGE_LUT_DATA_W_15_TO_8            (0x0814)
+#define SBL_REG_CABC_INTENSITY_7_TO_0                    (0x0900)
+#define SBL_REG_CABC_INTENSITY_11_TO_8                   (0x0904)
+#define SBL_REG_CABC_ICUT_SELECT                         (0x0908)
+#define SBL_REG_CABC_ICUT_MANUAL                         (0x090c)
+#define SBL_CABC_ICUT_OUT                                (0x0910)
+#define SBL_REG_CORE1_VC_CONTROL_0                       (0x0c00)
+#define SBL_REG_CORE1_IRDX_CONTROL_0                     (0x0c40)
+#define SBL_REG_CORE1_IRDX_CONTROL_1                     (0x0c44)
+#define SBL_REG_CORE1_IRDX_VARIANCE                      (0x0c4c)
+#define SBL_REG_CORE1_IRDX_SLOPE_MAX                     (0x0c50)
+#define SBL_REG_CORE1_IRDX_SLOPE_MIN                     (0x0c54)
+#define SBL_REG_CORE1_IRDX_BLACK_LEVEL_7_TO_0            (0x0c58)
+#define SBL_REG_CORE1_IRDX_BLACK_LEVEL_9_TO_8            (0x0c5c)
+#define SBL_REG_CORE1_IRDX_WHITE_LEVEL_7_TO_0            (0x0c60)
+#define SBL_REG_CORE1_IRDX_WHITE_LEVEL_9_TO_8            (0x0c64)
+#define SBL_REG_CORE1_IRDX_LIMIT_AMPL                    (0x0c68)
+#define SBL_REG_CORE1_IRDX_DITHER                        (0x0c6c)
+#define SBL_REG_CORE1_IRDX_STRENGTH_INROI_7_TO_0         (0x0c70)
+#define SBL_REG_CORE1_IRDX_STRENGTH_INROI_9_TO_8         (0x0c74)
+#define SBL_REG_CORE1_IRDX_STRENGTH_OUTROI_7_TO_0        (0x0c78)
+#define SBL_REG_CORE1_IRDX_STRENGTH_OUTROI_9_TO_8        (0x0c7c)
+#define SBL_CORE1_IRDX_ASYMMETRY_LUT_ADDR_I              (0x0c80)
+#define SBL_CORE1_IRDX_ASYMMETRY_LUT_DATA_W_7_TO_0       (0x0c84)
+#define SBL_CORE1_IRDX_ASYMMETRY_LUT_DATA_W_11_TO_8      (0x0c88)
+#define SBL_CORE1_IRDX_COLOR_LUT_ADDR_I                  (0x0cc0)
+#define SBL_CORE1_IRDX_COLOR_LUT_DATA_W_7_TO_0           (0x0cc4)
+#define SBL_CORE1_IRDX_COLOR_LUT_DATA_W_11_TO_8          (0x0cc8)
+#define SBL_REG_CORE1_IRDX_FILTER_CTRL                   (0x0d00)
+#define SBL_REG_CORE1_IRDX_SVARIANCE                     (0x0d04)
+#define SBL_REG_CORE1_IRDX_BRIGHTPR                      (0x0d08)
+#define SBL_REG_CORE1_IRDX_CONTRAST                      (0x0d0c)
+#define SBL_REG_CORE1_IRDX_DARKENH_7_TO_0                (0x0d10)
+#define SBL_REG_CORE1_IRDX_DARKENH_15_TO_8               (0x0d14)
+#define SBL_REG_CORE1_DTHR_CONTROL                       (0x0dc0)
+#define SBL_REG_CORE1_LOGO_TOP                           (0x0dd0)
+#define SBL_REG_CORE1_LOGO_LEFT                          (0x0dd4)
+#define SBL_REG_CORE1_CA_D_ARTITHRESH_7_TO_0             (0x0e00)
+#define SBL_REG_CORE1_CA_D_ARTITHRESH_9_TO_8             (0x0e04)
+#define SBL_CORE1_CA_STR_ATTEN_7_TO_0                    (0x0e10)
+#define SBL_CORE1_CA_STR_ATTEN_15_TO_8                   (0x0e14)
+#define SBL_CORE1_CA_STR_ATTEN_16                        (0x0e18)
+#define SBL_REG_CORE1_FRD_D_THRESH_7_TO_0                (0x0e20)
+#define SBL_REG_CORE1_FRD_D_THRESH_9_TO_8                (0x0e24)
+#define SBL_REG_CORE1_REG0_7_TO_0                        (0x0e28)
+#define SBL_REG_CORE1_REG0_15_TO_8                       (0x0e2c)
+#define SBL_REG_CORE1_REG1_7_TO_0                        (0x0e30)
+#define SBL_REG_CORE1_REG1_15_TO_8                       (0x0e34)
+#define SBL_REG_CORE1_REG2_7_TO_0                        (0x0e38)
+#define SBL_REG_CORE1_REG2_15_TO_8                       (0x0e3c)
+#define SBL_REG_CORE1_REG3_7_TO_0                        (0x0e40)
+#define SBL_REG_CORE1_REG3_15_TO_8                       (0x0e44)
+#define SBL_REG_CORE1_REG4_7_TO_0                        (0x0e48)
+#define SBL_REG_CORE1_REG4_15_TO_8                       (0x0e4c)
+#define SBL_REG_CORE1_REG5_7_TO_0                        (0x0e50)
+#define SBL_REG_CORE1_REG5_15_TO_8                       (0x0e54)
+#define SBL_CORE1_REG_OUT0_7_TO_0                        (0x0e58)
+#define SBL_CORE1_REG_OUT0_15_TO_8                       (0x0e5c)
+#define SBL_CORE1_REG_OUT1_7_TO_0                        (0x0e60)
+#define SBL_CORE1_REG_OUT1_15_TO_8                       (0x0e64)
+
+typedef struct dss_sbl {
+	int sbl_backlight_l;
+	int sbl_backlight_h;
+	int sbl_ambient_light_l;
+	int sbl_ambient_light_h;
+	int sbl_calibration_a_l;
+	int sbl_calibration_a_h;
+	int sbl_calibration_b_l;
+	int sbl_calibration_b_h;
+	int sbl_calibration_c_l;
+	int sbl_calibration_c_h;
+	int sbl_calibration_d_l;
+	int sbl_calibration_d_h;
+	int sbl_enable;
+} dss_sbl_t;
+
+/*******************************************************************************
+ ** DPP
+ */
+
+#define DPP_RD_SHADOW_SEL	(0x000)
+#define DPP_DEFAULT	(0x004)
+#define DPP_ID	(0x008)
+#define DPP_IMG_SIZE_BEF_SR	(0x00C)
+#define DPP_IMG_SIZE_AFT_SR	(0x010)
+#define DPP_SBL	(0x014)
+#define DPP_SBL_MEM_CTRL	(0x018)
+#define DPP_ARSR1P_MEM_CTRL	(0x01C)
+#define DPP_CLK_SEL	(0x020)
+#define DPP_CLK_EN	(0x024)
+#define DPP_DBG1_CNT	(0x028)
+#define DPP_DBG2_CNT	(0x02C)
+#define DPP_DBG1	(0x030)
+#define DPP_DBG2	(0x034)
+#define DPP_DBG3	(0x038)
+#define DPP_DBG4	(0x03C)
+#define DPP_INTS	(0x040)
+#define DPP_INT_MSK	(0x044)
+#define DPP_ARSR1P	(0x048)
+#define DPP_DBG_CNT  DPP_DBG1_CNT
+
+
+#define DPP_CLRBAR_CTRL (0x100)
+#define DPP_CLRBAR_1ST_CLR (0x104)
+#define DPP_CLRBAR_2ND_CLR (0x108)
+#define DPP_CLRBAR_3RD_CLR (0x10C)
+
+
+#define DPP_CLIP_TOP (0x180)
+#define DPP_CLIP_BOTTOM (0x184)
+#define DPP_CLIP_LEFT (0x188)
+#define DPP_CLIP_RIGHT (0x18C)
+#define DPP_CLIP_EN (0x190)
+#define DPP_CLIP_DBG (0x194)
+
+
+#define DITHER_PARA (0x000)
+#define DITHER_CTL (0x004)
+#define DITHER_MATRIX_PART1 (0x008)
+#define DITHER_MATRIX_PART0 (0x00C)
+#define DITHER_ERRDIFF_WEIGHT (0x010)
+#define DITHER_FRC_01_PART1 (0x014)
+#define DITHER_FRC_01_PART0 (0x018)
+#define DITHER_FRC_10_PART1 (0x01C)
+#define DITHER_FRC_10_PART0 (0x020)
+#define DITHER_FRC_11_PART1 (0x024)
+#define DITHER_FRC_11_PART0 (0x028)
+#define DITHER_MEM_CTRL (0x02C)
+#define DITHER_DBG0 (0x030)
+#define DITHER_DBG1 (0x034)
+#define DITHER_DBG2 (0x038)
+
+
+#define CSC10B_IDC0	(0x000)
+#define CSC10B_IDC1	(0x004)
+#define CSC10B_IDC2	(0x008)
+#define CSC10B_ODC0	(0x00C)
+#define CSC10B_ODC1	(0x010)
+#define CSC10B_ODC2	(0x014)
+#define CSC10B_P00	(0x018)
+#define CSC10B_P01	(0x01C)
+#define CSC10B_P02	(0x020)
+#define CSC10B_P10	(0x024)
+#define CSC10B_P11	(0x028)
+#define CSC10B_P12	(0x02C)
+#define CSC10B_P20	(0x030)
+#define CSC10B_P21	(0x034)
+#define CSC10B_P22	(0x038)
+#define CSC10B_MODULE_EN	(0x03C)
+#define CSC10B_MPREC	(0x040)
+
+
+#define GAMA_EN	(0x000)
+#define GAMA_MEM_CTRL	(0x004)
+
+
+#define ACM_EN	(0x000)
+#define ACM_SATA_OFFSET	(0x004)
+#define ACM_HUESEL	(0x008)
+#define ACM_CSC_IDC0	(0x00C)
+#define ACM_CSC_IDC1	(0x010)
+#define ACM_CSC_IDC2	(0x014)
+#define ACM_CSC_P00	(0x018)
+#define ACM_CSC_P01	(0x01C)
+#define ACM_CSC_P02	(0x020)
+#define ACM_CSC_P10	(0x024)
+#define ACM_CSC_P11	(0x028)
+#define ACM_CSC_P12	(0x02C)
+#define ACM_CSC_P20	(0x030)
+#define ACM_CSC_P21	(0x034)
+#define ACM_CSC_P22	(0x038)
+#define ACM_CSC_MRREC	(0x03C)
+#define ACM_R0_H	(0x040)
+#define ACM_R1_H	(0x044)
+#define ACM_R2_H	(0x048)
+#define ACM_R3_H	(0x04C)
+#define ACM_R4_H	(0x050)
+#define ACM_R5_H	(0x054)
+#define ACM_R6_H	(0x058)
+#define ACM_LUT_DIS0	(0x05C)
+#define ACM_LUT_DIS1	(0x060)
+#define ACM_LUT_DIS2	(0x064)
+#define ACM_LUT_DIS3	(0x068)
+#define ACM_LUT_DIS4	(0x06C)
+#define ACM_LUT_DIS5	(0x070)
+#define ACM_LUT_DIS6	(0x074)
+#define ACM_LUT_DIS7	(0x078)
+#define ACM_LUT_PARAM0	(0x07C)
+#define ACM_LUT_PARAM1	(0x080)
+#define ACM_LUT_PARAM2	(0x084)
+#define ACM_LUT_PARAM3	(0x088)
+#define ACM_LUT_PARAM4	(0x08C)
+#define ACM_LUT_PARAM5	(0x090)
+#define ACM_LUT_PARAM6	(0x094)
+#define ACM_LUT_PARAM7	(0x098)
+#define ACM_LUT_SEL	(0x09C)
+#define ACM_MEM_CTRL	(0x0A0)
+#define ACM_DEBUG_TOP	(0x0A4)
+#define ACM_DEBUG_CFG	(0x0A8)
+#define ACM_DEBUG_W	(0x0AC)
+
+
+#define ACE_EN	(0x000)
+#define ACE_SKIN_CFG	(0x004)
+#define ACE_LUT_SEL	(0x008)
+#define ACE_HIST_IND	(0x00C)
+#define ACE_ACTIVE	(0x010)
+#define ACE_DBG	(0x014)
+#define ACE_MEM_CTRL	(0x018)
+#define ACE_IN_SEL	(0x01C)
+#define ACE_R2Y	(0x020)
+#define ACE_G2Y	(0x024)
+#define ACE_B2Y	(0x028)
+#define ACE_Y_OFFSET	(0x02C)
+#define ACE_Y_CEN	(0x030)
+#define ACE_U_CEN	(0x034)
+#define ACE_V_CEN	(0x038)
+#define ACE_Y_EXT	(0x03C)
+#define ACE_U_EXT	(0x040)
+#define ACE_V_EXT	(0x044)
+#define ACE_Y_ATTENU 	(0x048)
+#define ACE_U_ATTENU	(0x04C)
+#define ACE_V_ATTENU	(0x050)
+#define ACE_ROTA	(0x054)
+#define ACE_ROTB 	(0x058)
+#define ACE_Y_CORE	(0x05C)
+#define ACE_U_CORE	(0x060)
+#define ACE_V_CORE	(0x064)
+
+
+#define LCP_XCC_COEF_00	(0x000)
+#define LCP_XCC_COEF_01	(0x004)
+#define LCP_XCC_COEF_02	(0x008)
+#define LCP_XCC_COEF_03	(0x00C)
+#define LCP_XCC_COEF_10	(0x010)
+#define LCP_XCC_COEF_11	(0x014)
+#define LCP_XCC_COEF_12	(0x018)
+#define LCP_XCC_COEF_13	(0x01C)
+#define LCP_XCC_COEF_20	(0x020)
+#define LCP_XCC_COEF_21	(0x024)
+#define LCP_XCC_COEF_22	(0x028)
+#define LCP_XCC_COEF_23	(0x02C)
+#define LCP_GMP_BYPASS_EN	(0x030)
+#define LCP_XCC_BYPASS_EN	(0x034)
+#define LCP_DEGAMA_EN	(0x038)
+#define LCP_DEGAMA_MEM_CTRL	(0x03C)
+#define LCP_GMP_MEM_CTRL	(0x040)
+
+
+typedef struct dss_arsr1p {
+	uint32_t ihleft;
+	uint32_t ihright;
+	uint32_t ihleft1;
+	uint32_t ihright1;
+	uint32_t ivtop;
+	uint32_t ivbottom;
+	uint32_t uv_offset;
+	uint32_t ihinc;
+	uint32_t ivinc;
+	uint32_t mode;
+	uint32_t format;
+
+	uint32_t skin_thres_y;
+	uint32_t skin_thres_u;
+	uint32_t skin_thres_v;
+	uint32_t skin_expected;
+	uint32_t skin_cfg;
+	uint32_t shoot_cfg1;
+	uint32_t shoot_cfg2;
+	uint32_t sharp_cfg1;
+	uint32_t sharp_cfg2;
+	uint32_t sharp_cfg3;
+	uint32_t sharp_cfg4;
+	uint32_t sharp_cfg5;
+	uint32_t sharp_cfg6;
+	uint32_t sharp_cfg7;
+	uint32_t sharp_cfg8;
+	uint32_t sharp_cfg9;
+	uint32_t sharp_cfg10;
+	uint32_t sharp_cfg11;
+	uint32_t diff_ctrl;
+	uint32_t lsc_cfg1;
+	uint32_t lsc_cfg2;
+	uint32_t lsc_cfg3;
+	uint32_t force_clk_on_cfg;
+
+	uint32_t dpp_img_hrz_bef_sr;
+	uint32_t dpp_img_vrt_bef_sr;
+	uint32_t dpp_img_hrz_aft_sr;
+	uint32_t dpp_img_vrt_aft_sr;
+} dss_arsr1p_t;
+
+#define ARSR1P_INC_FACTOR (65536)
+
+#define ARSR1P_IHLEFT		(0x000)
+#define ARSR1P_IHRIGHT		(0x004)
+#define ARSR1P_IHLEFT1		(0x008)
+#define ARSR1P_IHRIGHT1		(0x00C)
+#define ARSR1P_IVTOP		(0x010)
+#define ARSR1P_IVBOTTOM		(0x014)
+#define ARSR1P_UV_OFFSET		(0x018)
+#define ARSR1P_IHINC		(0x01C)
+#define ARSR1P_IVINC		(0x020)
+#define ARSR1P_MODE			(0x024)
+#define ARSR1P_FORMAT		(0x028)
+#define ARSR1P_SKIN_THRES_Y		(0x02C)
+#define ARSR1P_SKIN_THRES_U		(0x030)
+#define ARSR1P_SKIN_THRES_V		(0x034)
+#define ARSR1P_SKIN_EXPECTED	(0x038)
+#define ARSR1P_SKIN_CFG			(0x03C)
+#define ARSR1P_SHOOT_CFG1		(0x040)
+#define ARSR1P_SHOOT_CFG2		(0x044)
+#define ARSR1P_SHARP_CFG1		(0x048)
+#define ARSR1P_SHARP_CFG2		(0x04C)
+#define ARSR1P_SHARP_CFG3		(0x050)
+#define ARSR1P_SHARP_CFG4		(0x054)
+#define ARSR1P_SHARP_CFG5		(0x058)
+#define ARSR1P_SHARP_CFG6		(0x05C)
+#define ARSR1P_SHARP_CFG7		(0x060)
+#define ARSR1P_SHARP_CFG8		(0x064)
+#define ARSR1P_SHARP_CFG9		(0x068)
+#define ARSR1P_SHARP_CFG10		(0x06C)
+#define ARSR1P_SHARP_CFG11		(0x070)
+#define ARSR1P_DIFF_CTRL		(0x074)
+#define ARSR1P_LSC_CFG1		(0x078)
+#define ARSR1P_LSC_CFG2		(0x07C)
+#define ARSR1P_LSC_CFG3		(0x080)
+#define ARSR1P_FORCE_CLK_ON_CFG		(0x084)
+
+/*******************************************************************************
+ ** BIT EXT
+ */
+#define BIT_EXT0_CTL (0x000)
+
+
+#define U_GAMA_R_COEF	(0x000)
+#define U_GAMA_G_COEF	(0x400)
+#define U_GAMA_B_COEF	(0x800)
+#define U_GAMA_R_LAST_COEF (0x200)
+#define U_GAMA_G_LAST_COEF (0x600)
+#define U_GAMA_B_LAST_COEF (0xA00)
+
+
+#define ACM_U_H_COEF	(0x000)
+#define ACM_U_SATA_COEF	(0x200)
+#define ACM_U_SATR0_COEF	(0x300)
+#define ACM_U_SATR1_COEF	(0x340)
+#define ACM_U_SATR2_COEF	(0x380)
+#define ACM_U_SATR3_COEF	(0x3C0)
+#define ACM_U_SATR4_COEF	(0x400)
+#define ACM_U_SATR5_COEF	(0x440)
+#define ACM_U_SATR6_COEF	(0x480)
+#define ACM_U_SATR7_COEF	(0x4C0)
+
+
+#define LCP_U_GMP_COEF	(0x0000)
+#define LCP_U_DEGAMA_R_COEF	(0x5000)
+#define LCP_U_DEGAMA_G_COEF	(0x5400)
+#define LCP_U_DEGAMA_B_COEF	(0x5800)
+#define LCP_U_DEGAMA_R_LAST_COEF (0x5200)
+#define LCP_U_DEGAMA_G_LAST_COEF (0x5600)
+#define LCP_U_DEGAMA_B_LAST_COEF (0x5A00)
+
+
+#define ACE_HIST0	(0x000)
+#define ACE_HIST1	(0x400)
+#define ACE_LUT0	(0x800)
+#define ACE_LUT1	(0xA00)
+
+
+#define ARSR1P_LSC_GAIN		(0x084)
+#define ARSR1P_COEFF_H_Y0	(0x0F0)
+#define ARSR1P_COEFF_H_Y1	(0x114)
+#define ARSR1P_COEFF_V_Y0	(0x138)
+#define ARSR1P_COEFF_V_Y1	(0x15C)
+#define ARSR1P_COEFF_H_UV0	(0x180)
+#define ARSR1P_COEFF_H_UV1	(0x1A4)
+#define ARSR1P_COEFF_V_UV0	(0x1C8)
+#define ARSR1P_COEFF_V_UV1	(0x1EC)
+
+
+#define HIACE_INT_STAT (0x0000)
+#define HIACE_INT_UNMASK (0x0004)
+#define HIACE_BYPASS_ACE (0x0008)
+#define HIACE_BYPASS_ACE_STAT (0x000c)
+#define HIACE_UPDATE_LOCAL (0x0010)
+#define HIACE_LOCAL_VALID (0x0014)
+#define HIACE_GAMMA_AB_SHADOW (0x0018)
+#define HIACE_GAMMA_AB_WORK (0x001c)
+#define HIACE_GLOBAL_HIST_AB_SHADOW (0x0020)
+#define HIACE_GLOBAL_HIST_AB_WORK (0x0024)
+#define HIACE_IMAGE_INFO (0x0030)
+#define HIACE_HALF_BLOCK_H_W (0x0034)
+#define HIACE_XYWEIGHT (0x0038)
+#define HIACE_LHIST_SFT (0x003c)
+#define HIACE_HUE (0x0050)
+#define HIACE_SATURATION (0x0054)
+#define HIACE_VALUE (0x0058)
+#define HIACE_SKIN_GAIN (0x005c)
+#define HIACE_UP_LOW_TH (0x0060)
+#define HIACE_UP_CNT (0x0070)
+#define HIACE_LOW_CNT (0x0074)
+#define HIACE_GLOBAL_HIST_LUT_ADDR (0x0080)
+#define HIACE_LHIST_EN (0x0100)
+#define HIACE_LOCAL_HIST_VxHy_2z_2z1 (0x0104)
+#define HIACE_GAMMA_EN (0x0108)
+#define HIACE_GAMMA_VxHy_3z2_3z1_3z_W (0x010c)
+#define HIACE_GAMMA_EN_HV_R (0x0110)
+#define HIACE_GAMMA_VxHy_3z2_3z1_3z_R (0x0114)
+#define HIACE_INIT_GAMMA (0x0120)
+#define HIACE_MANUAL_RELOAD (0x0124)
+#define HIACE_RAMCLK_FUNC (0x0128)
+#define HIACE_CLK_GATE (0x012c)
+#define HIACE_GAMMA_RAM_A_CFG_MEM_CTRL (0x0130)
+#define HIACE_GAMMA_RAM_B_CFG_MEM_CTRL (0x0134)
+#define HIACE_LHIST_RAM_CFG_MEM_CTRL (0x0138)
+#define HIACE_GAMMA_RAM_A_CFG_PM_CTRL (0x0140)
+#define HIACE_GAMMA_RAM_B_CFG_PM_CTRL (0x0144)
+#define HIACE_LHIST_RAM_CFG_PM_CTRL (0x0148)
+
+/*******************************************************************************
+ ** IFBC
+ */
+#define IFBC_SIZE	(0x0000)
+#define IFBC_CTRL	(0x0004)
+#define IFBC_HIMAX_CTRL0	(0x0008)
+#define IFBC_HIMAX_CTRL1	(0x000C)
+#define IFBC_HIMAX_CTRL2	(0x0010)
+#define IFBC_HIMAX_CTRL3	(0x0014)
+#define IFBC_EN	(0x0018)
+#define IFBC_MEM_CTRL	(0x001C)
+#define IFBC_INSERT	(0x0020)
+#define IFBC_HIMAX_TEST_MODE	(0x0024)
+#define IFBC_CORE_GT	(0x0028)
+#define IFBC_PM_CTRL	(0x002C)
+#define IFBC_RD_SHADOW	(0x0030)
+#define IFBC_ORISE_CTL	(0x0034)
+#define IFBC_ORSISE_DEBUG0	(0x0038)
+#define IFBC_ORSISE_DEBUG1	(0x003C)
+#define IFBC_RSP_COMP_TEST	(0x0040)
+#define IFBC_CLK_SEL	(0x044)
+#define IFBC_CLK_EN	(0x048)
+#define IFBC_PAD	(0x004C)
+#define IFBC_REG_DEFAULT	(0x0050)
+
+/*******************************************************************************
+ ** DSC
+ */
+#define DSC_VERSION	(0x0000)
+#define DSC_PPS_IDENTIFIER	(0x0004)
+#define DSC_EN	(0x0008)
+#define DSC_CTRL	(0x000C)
+#define DSC_PIC_SIZE	(0x0010)
+#define DSC_SLICE_SIZE	(0x0014)
+#define DSC_CHUNK_SIZE	(0x0018)
+#define DSC_INITIAL_DELAY	(0x001C)
+#define DSC_RC_PARAM0	(0x0020)
+#define DSC_RC_PARAM1	(0x0024)
+#define DSC_RC_PARAM2	(0x0028)
+#define DSC_RC_PARAM3	(0x002C)
+#define DSC_FLATNESS_QP_TH	(0x0030)
+#define DSC_RC_PARAM4	(0x0034)
+#define DSC_RC_PARAM5	(0x0038)
+#define DSC_RC_BUF_THRESH0	(0x003C)
+#define DSC_RC_BUF_THRESH1	(0x0040)
+#define DSC_RC_BUF_THRESH2	(0x0044)
+#define DSC_RC_BUF_THRESH3	(0x0048)
+#define DSC_RC_RANGE_PARAM0	(0x004C)
+#define DSC_RC_RANGE_PARAM1	(0x0050)
+#define DSC_RC_RANGE_PARAM2	(0x0054)
+#define DSC_RC_RANGE_PARAM3	(0x0058)
+#define DSC_RC_RANGE_PARAM4	(0x005C)
+#define DSC_RC_RANGE_PARAM5	(0x0060)
+#define DSC_RC_RANGE_PARAM6	(0x0064)
+#define DSC_RC_RANGE_PARAM7	(0x0068)
+#define DSC_ADJUSTMENT_BITS	(0x006C)
+#define DSC_BITS_PER_GRP	(0x0070)
+#define DSC_MULTI_SLICE_CTL	(0x0074)
+#define DSC_OUT_CTRL	(0x0078)
+#define DSC_CLK_SEL	(0x007C)
+#define DSC_CLK_EN	(0x0080)
+#define DSC_MEM_CTRL	(0x0084)
+#define DSC_ST_DATAIN	(0x0088)
+#define DSC_ST_DATAOUT	(0x008C)
+#define DSC0_ST_SLC_POS	(0x0090)
+#define DSC1_ST_SLC_POS	(0x0094)
+#define DSC0_ST_PIC_POS	(0x0098)
+#define DSC1_ST_PIC_POS	(0x009C)
+#define DSC0_ST_FIFO	(0x00A0)
+#define DSC1_ST_FIFO	(0x00A4)
+#define DSC0_ST_LINEBUF	(0x00A8)
+#define DSC1_ST_LINEBUF	(0x00AC)
+#define DSC_ST_ITFC	(0x00B0)
+#define DSC_RD_SHADOW_SEL	(0x00B4)
+#define DSC_REG_DEFAULT	(0x00B8)
+
+/*******************************************************************************
+ ** LDI
+ */
+#define LDI_DPI0_HRZ_CTRL0	(0x0000)
+#define LDI_DPI0_HRZ_CTRL1	(0x0004)
+#define LDI_DPI0_HRZ_CTRL2	(0x0008)
+#define LDI_VRT_CTRL0	(0x000C)
+#define LDI_VRT_CTRL1	(0x0010)
+#define LDI_VRT_CTRL2	(0x0014)
+#define LDI_PLR_CTRL	(0x0018)
+#define LDI_SH_MASK_INT	(0x001C)
+#define LDI_3D_CTRL	(0x0020)
+#define LDI_CTRL	(0x0024)
+#define LDI_WORK_MODE	(0x0028)
+#define LDI_DE_SPACE_LOW	(0x002C)
+#define LDI_DSI_CMD_MOD_CTRL	(0x0030)
+#define LDI_DSI_TE_CTRL	(0x0034)
+#define LDI_DSI_TE_HS_NUM	(0x0038)
+#define LDI_DSI_TE_HS_WD	(0x003C)
+#define LDI_DSI_TE_VS_WD	(0x0040)
+#define LDI_FRM_MSK	(0x0044)
+#define LDI_FRM_MSK_UP	(0x0048)
+#define LDI_VINACT_MSK_LEN	(0x0050)
+#define LDI_VSTATE	(0x0054)
+#define LDI_DPI0_HSTATE	(0x0058)
+#define LDI_DPI1_HSTATE	(0x005C)
+#define LDI_CMD_EVENT_SEL	(0x0060)
+#define LDI_SRAM_LP_CTRL	(0x0064)
+#define LDI_ITF_RD_SHADOW	(0x006C)
+#define LDI_DPI1_HRZ_CTRL0	(0x00F0)
+#define LDI_DPI1_HRZ_CTRL1	(0x00F4)
+#define LDI_DPI1_HRZ_CTRL2	(0x00F8)
+#define LDI_OVERLAP_SIZE	(0x00FC)
+#define LDI_MEM_CTRL	(0x0100)
+#define LDI_PM_CTRL	(0x0104)
+#define LDI_CLK_SEL	(0x0108)
+#define LDI_CLK_EN	(0x010C)
+#define LDI_IF_BYPASS	(0x0110)
+#define LDI_FRM_VALID_DBG (0x0118)
+/* LDI GLB*/
+#define LDI_PXL0_DIV2_GT_EN (0x0210)
+#define LDI_PXL0_DIV4_GT_EN (0x0214)
+#define LDI_PXL0_GT_EN (0x0218)
+#define LDI_PXL0_DSI_GT_EN (0x021C)
+#define LDI_PXL0_DIVXCFG (0x0220)
+#define LDI_DSI1_CLK_SEL (0x0224)
+#define LDI_VESA_CLK_SEL (0x0228)
+/* DSI1 RST*/
+#define LDI_DSI1_RST_SEL (0x0238)
+/* LDI INTERRUPT*/
+#define LDI_MCU_ITF_INTS (0x0240)
+#define LDI_MCU_ITF_INT_MSK (0x0244)
+#define LDI_CPU_ITF_INTS (0x0248)
+#define LDI_CPU_ITF_INT_MSK (0x024C)
+/* LDI MODULE CLOCK GATING*/
+#define LDI_MODULE_CLK_SEL (0x0258)
+#define LDI_MODULE_CLK_EN (0x025C)
+
+/*******************************************************************************
+ ** MIPI DSI
+ */
+#define MIPIDSI_VERSION_OFFSET	(0x0000)
+#define MIPIDSI_PWR_UP_OFFSET	(0x0004)
+#define MIPIDSI_CLKMGR_CFG_OFFSET	(0x0008)
+#define MIPIDSI_DPI_VCID_OFFSET	(0x000c)
+#define MIPIDSI_DPI_COLOR_CODING_OFFSET	(0x0010)
+#define MIPIDSI_DPI_CFG_POL_OFFSET	(0x0014)
+#define MIPIDSI_DPI_LP_CMD_TIM_OFFSET	(0x0018)
+#define MIPIDSI_PCKHDL_CFG_OFFSET	(0x002c)
+#define MIPIDSI_GEN_VCID_OFFSET	(0x0030)
+#define MIPIDSI_MODE_CFG_OFFSET	(0x0034)
+#define MIPIDSI_VID_MODE_CFG_OFFSET	(0x0038)
+#define MIPIDSI_VID_PKT_SIZE_OFFSET	(0x003c)
+#define MIPIDSI_VID_NUM_CHUNKS_OFFSET	(0x0040)
+#define MIPIDSI_VID_NULL_SIZE_OFFSET	(0x0044)
+#define MIPIDSI_VID_HSA_TIME_OFFSET	(0x0048)
+#define MIPIDSI_VID_HBP_TIME_OFFSET	(0x004c)
+#define MIPIDSI_VID_HLINE_TIME_OFFSET	(0x0050)
+#define MIPIDSI_VID_VSA_LINES_OFFSET	(0x0054)
+#define MIPIDSI_VID_VBP_LINES_OFFSET	(0x0058)
+#define MIPIDSI_VID_VFP_LINES_OFFSET	(0x005c)
+#define MIPIDSI_VID_VACTIVE_LINES_OFFSET	(0x0060)
+#define MIPIDSI_EDPI_CMD_SIZE_OFFSET	(0x0064)
+#define MIPIDSI_CMD_MODE_CFG_OFFSET	(0x0068)
+#define MIPIDSI_GEN_HDR_OFFSET	(0x006c)
+#define MIPIDSI_GEN_PLD_DATA_OFFSET	(0x0070)
+#define MIPIDSI_CMD_PKT_STATUS_OFFSET	(0x0074)
+#define MIPIDSI_TO_CNT_CFG_OFFSET	(0x0078)
+#define MIPIDSI_HS_RD_TO_CNT_OFFSET	(0x007C)
+#define MIPIDSI_LP_RD_TO_CNT_OFFSET	(0x0080)
+#define MIPIDSI_HS_WR_TO_CNT_OFFSET	(0x0084)
+#define MIPIDSI_LP_WR_TO_CNT_OFFSET	(0x0088)
+#define MIPIDSI_BTA_TO_CNT_OFFSET	(0x008C)
+#define MIPIDSI_SDF_3D_OFFSET	(0x0090)
+#define MIPIDSI_LPCLK_CTRL_OFFSET	(0x0094)
+#define MIPIDSI_PHY_TMR_LPCLK_CFG_OFFSET	(0x0098)
+#define MIPIDSI_PHY_TMR_CFG_OFFSET	(0x009c)
+#define MIPIDSI_PHY_RSTZ_OFFSET	(0x00a0)
+#define MIPIDSI_PHY_IF_CFG_OFFSET	(0x00a4)
+#define MIPIDSI_PHY_ULPS_CTRL_OFFSET	(0x00a8)
+#define MIPIDSI_PHY_TX_TRIGGERS_OFFSET	(0x00ac)
+#define MIPIDSI_PHY_STATUS_OFFSET	(0x00b0)
+#define MIPIDSI_PHY_TST_CTRL0_OFFSET	(0x00b4)
+#define MIPIDSI_PHY_TST_CTRL1_OFFSET	(0x00b8)
+#define MIPIDSI_INT_ST0_OFFSET	(0x00bc)
+#define MIPIDSI_INT_ST1_OFFSET	(0x00c0)
+#define MIPIDSI_INT_MSK0_OFFSET	(0x00c4)
+#define MIPIDSI_INT_MSK1_OFFSET	(0x00c8)
+#define INT_FORCE0	(0x00D8)
+#define INT_FORCE1	(0x00DC)
+#define MIPIDSI_DSC_PARAMETER_OFFSET	(0x00f0)
+#define MIPIDSI_PHY_TMR_RD_CFG_OFFSET	(0x00f4)
+#define VID_SHADOW_CTRL	(0x0100)
+#define DPI_VCID_ACT	(0x010C)
+#define DPI_COLOR_CODING_ACT	(0x0110)
+#define DPI_LP_CMD_TIM_ACT	(0x0118)
+#define VID_MODE_CFG_ACT	(0x0138)
+#define VID_PKT_SIZE_ACT	(0x013C)
+#define VID_NUM_CHUNKS_ACT	(0x0140)
+#define VID_NULL_SIZE_ACT	(0x0144)
+#define VID_HSA_TIME_ACT	(0x0148)
+#define VID_HBP_TIME_ACT	(0x014C)
+#define VID_HLINE_TIME_ACT	(0x0150)
+#define VID_VSA_LINES_ACT	(0x0154)
+#define VID_VBP_LINES_ACT	(0x0158)
+#define VID_VFP_LINES_ACT	(0x015C)
+#define VID_VACTIVE_LINES_ACT	(0x0160)
+#define SDF_3D_ACT	(0x0190)
+
+/*******************************************************************************
+ ** MMBUF
+ */
+#define SMC_LOCK	(0x0000)
+#define SMC_MEM_LP	(0x0004)
+#define SMC_GCLK_CS	(0x000C)
+#define SMC_QOS_BACKDOOR	(0x0010)
+#define SMC_DFX_WCMD_CNT_1ST	(0x0014)
+#define SMC_DFX_WCMD_CNT_2ND	(0x0018)
+#define SMC_DFX_WCMD_CNT_3RD	(0x001C)
+#define SMC_DFX_WCMD_CNT_4TH	(0x0020)
+#define SMC_DFX_RCMD_CNT_1ST	(0x0024)
+#define SMC_DFX_RCMD_CNT_2ND	(0x0028)
+#define SMC_DFX_RCMD_CNT_3RD	(0x002C)
+#define SMC_DFX_RCMD_CNT_4TH	(0x0030)
+#define SMC_CS_IDLE	(0x0034)
+#define SMC_DFX_BFIFO_CNT0	(0x0038)
+#define SMC_DFX_RDFIFO_CNT1	(0x003C)
+#define SMC_SP_SRAM_STATE0	(0x0040)
+#define SMC_SP_SRAM_STATE1	(0x0044)
+
+/*******************************************************************************
+ ** dirty_region_updt
+ */
+typedef struct dirty_region_updt {
+	uint32_t dbuf_frm_size;
+	uint32_t dbuf_frm_hsize;
+	uint32_t dpp_img_hrz_bef_sr;
+	uint32_t dpp_img_vrt_bef_sr;
+	uint32_t dpp_img_hrz_aft_sr;
+	uint32_t dpp_img_vrt_aft_sr;
+	uint32_t ldi_dpi0_hrz_ctrl0;
+	uint32_t ldi_dpi0_hrz_ctrl1;
+	uint32_t ldi_dpi0_hrz_ctrl2;
+	uint32_t ldi_dpi1_hrz_ctrl0;
+	uint32_t ldi_dpi1_hrz_ctrl1;
+	uint32_t ldi_dpi1_hrz_ctrl2;
+	uint32_t ldi_vrt_ctrl0;
+	uint32_t ldi_vrt_ctrl1;
+	uint32_t ldi_vrt_ctrl2;
+	uint32_t ldi_ctrl;
+	uint32_t ifbc_size;
+	uint32_t edpi_cmd_size;
+	dss_arsr1p_t s_arsr1p;
+} dirty_region_updt_t;
+
+/*******************************************************************************
+ ** dss module reg
+ */
+typedef struct dss_module_reg {
+	char __iomem *mif_ch_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *aif_ch_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *aif1_ch_base[DSS_CHN_MAX_DEFINE];
+	dss_mctl_ch_base_t mctl_ch_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *dma_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *dfc_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *scl_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *scl_lut_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *arsr2p_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *arsr2p_lut_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *post_clip_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *pcsc_base[DSS_CHN_MAX_DEFINE];
+	char __iomem *csc_base[DSS_CHN_MAX_DEFINE];
+
+	char __iomem *ov_base[DSS_OVL_IDX_MAX];
+	char __iomem *mctl_base[DSS_MCTL_IDX_MAX];
+	char __iomem *mctl_sys_base;
+	char __iomem *smmu_base;
+	char __iomem *post_scf_base;
+
+	dss_mif_t mif[DSS_CHN_MAX_DEFINE];
+	dss_aif_t aif[DSS_CHN_MAX_DEFINE];
+	dss_aif_t aif1[DSS_CHN_MAX_DEFINE];
+	dss_aif_bw_t aif_bw[DSS_CHN_MAX_DEFINE];
+	dss_aif_bw_t aif1_bw[DSS_CHN_MAX_DEFINE];
+	dss_rdma_t rdma[DSS_CHN_MAX_DEFINE];
+	dss_wdma_t wdma[DSS_CHN_MAX_DEFINE];
+	dss_dfc_t dfc[DSS_CHN_MAX_DEFINE];
+	dss_scl_t scl[DSS_CHN_MAX_DEFINE];
+	dss_arsr2p_t arsr2p[DSS_CHN_MAX_DEFINE];
+	dss_post_clip_t post_clip[DSS_CHN_MAX_DEFINE];
+	dss_csc_t pcsc[DSS_CHN_MAX_DEFINE];
+	dss_csc_t csc[DSS_CHN_MAX_DEFINE];
+	dss_ovl_t ov[DSS_OVL_IDX_MAX];
+	dss_mctl_t mctl[DSS_MCTL_IDX_MAX];
+	dss_mctl_ch_t mctl_ch[DSS_CHN_MAX_DEFINE];
+	dss_mctl_sys_t mctl_sys;
+	dss_smmu_t smmu;
+	dirty_region_updt_t dirty_region_updt;
+	dss_arsr1p_t post_scf;
+
+	uint8_t mif_used[DSS_CHN_MAX_DEFINE];
+	uint8_t aif_ch_used[DSS_CHN_MAX_DEFINE];
+	uint8_t aif1_ch_used[DSS_CHN_MAX_DEFINE];
+	uint8_t dma_used[DSS_CHN_MAX_DEFINE];
+	uint8_t dfc_used[DSS_CHN_MAX_DEFINE];
+	uint8_t scl_used[DSS_CHN_MAX_DEFINE];
+	uint8_t arsr2p_used[DSS_CHN_MAX_DEFINE];
+	uint8_t arsr2p_effect_used[DSS_CHN_MAX_DEFINE];
+	uint8_t post_cilp_used[DSS_CHN_MAX_DEFINE];
+	uint8_t pcsc_used[DSS_CHN_MAX_DEFINE];
+	uint8_t csc_used[DSS_CHN_MAX_DEFINE];
+	uint8_t ov_used[DSS_OVL_IDX_MAX];
+	uint8_t ch_reg_default_used[DSS_CHN_MAX_DEFINE];
+	uint8_t mctl_used[DSS_MCTL_IDX_MAX];
+	uint8_t mctl_ch_used[DSS_CHN_MAX_DEFINE];
+	uint8_t mctl_sys_used;
+	uint8_t smmu_used;
+	uint8_t dirty_region_updt_used;
+	uint8_t post_scf_used;
+} dss_module_reg_t;
+
+typedef struct dss_mmbuf_info {
+	uint32_t mm_base[DSS_CHN_MAX_DEFINE];
+	uint32_t mm_size[DSS_CHN_MAX_DEFINE];
+
+	uint8_t mm_used[DSS_CHN_MAX_DEFINE];
+} dss_mmbuf_info_t;
+
+#endif				/* HISI_DSS_REGS_H */
-- 
2.12.0-rc0

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