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Message-Id: <1486595685-10232-5-git-send-email-daniel.lezcano@linaro.org>
Date: Thu, 9 Feb 2017 00:14:39 +0100
From: Daniel Lezcano <daniel.lezcano@...aro.org>
To: tglx@...utronix.de
Cc: Chris Brandt <chris.brandt@...esas.com>,
Rob Herring <robh@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Geert Uytterhoeven <geert+renesas@...der.be>,
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS), linux-kernel@...r.kernel.org (open list)
Subject: [PATCH 05/10] clocksource/drivers/ostm: Document renesas-ostm timer DT bindings
From: Chris Brandt <chris.brandt@...esas.com>
Signed-off-by: Chris Brandt <chris.brandt@...esas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
Acked-by: Rob Herring <robh@...nel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@...aro.org>
---
.../devicetree/bindings/timer/renesas,ostm.txt | 30 ++++++++++++++++++++++
1 file changed, 30 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/renesas,ostm.txt
diff --git a/Documentation/devicetree/bindings/timer/renesas,ostm.txt b/Documentation/devicetree/bindings/timer/renesas,ostm.txt
new file mode 100644
index 0000000..be3ae0f
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,ostm.txt
@@ -0,0 +1,30 @@
+* Renesas OS Timer (OSTM)
+
+The OSTM is a multi-channel 32-bit timer/counter with fixed clock
+source that can operate in either interval count down timer or free-running
+compare match mode.
+
+Channels are independent from each other.
+
+Required Properties:
+
+ - compatible: must be one or more of the following:
+ - "renesas,r7s72100-ostm" for the r7s72100 OSTM
+ - "renesas,ostm" for any OSTM
+ This is a fallback for the above renesas,*-ostm entries
+
+ - reg: base address and length of the register block for a timer channel.
+
+ - interrupts: interrupt specifier for the timer channel.
+
+ - clocks: clock specifier for the timer channel.
+
+Example: R7S72100 (RZ/A1H) OSTM node
+
+ ostm0: timer@...ec000 {
+ compatible = "renesas,r7s72100-ostm", "renesas,ostm";
+ reg = <0xfcfec000 0x30>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
+ power-domains = <&cpg_clocks>;
+ };
--
2.7.4
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