linux-kernel - Re: [GIT PULL] PCI fixes for v4.10

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20170209150950.GA11905@bhelgaas-glaptop.roam.corp.google.com>
Date:   Thu, 9 Feb 2017 09:09:50 -0600
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Lukas Wunner <lukas@...ner.de>
Cc:     Linus Torvalds <torvalds@...ux-foundation.org>,
        linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
        Bart Van Assche <bart.vanassche@...disk.com>,
        Christoph Hellwig <hch@....de>,
        Yinghai Lu <yinghai@...nel.org>,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
        Mika Westerberg <mika.westerberg@...ux.intel.com>,
        Ashok Raj <ashok.raj@...el.com>,
        Keith Busch <keith.busch@...el.com>
Subject: Re: [GIT PULL] PCI fixes for v4.10

[+cc Ashok, Keith]

On Thu, Feb 09, 2017 at 05:06:48AM +0100, Lukas Wunner wrote:
> On Wed, Feb 08, 2017 at 01:22:56PM -0600, Bjorn Helgaas wrote:
> > Bjorn Helgaas (1):
> >       Revert "PCI: pciehp: Add runtime PM support for PCIe hotplug ports"
> 
> What's the rationale for reverting this?
> 
> You've received patches to fix the issue on both affected machines,
> so a revert seems unnecessary:
> 
> https://patchwork.kernel.org/patch/9557113/
> https://patchwork.kernel.org/patch/9562007/

I don't think we've gotten to the root cause of the problem yet,
and I don't want to throw in fixes at the last minute without a better
understanding of it.

PCIe hotplug hardware is not very complicated, it hasn't changed in
many years, and at least for the Intel hardware in question, is
generally pretty well-tested with Windows.  So I want to be careful
about asserting that this new piece of hardware is broken.

I think pciehp is unnecessarily complicated, and we do have known
synchronization issues with it, e.g., [1] [2].  It seems possible that
if we poked a little deeper, we would find that the hardware is
actually working correctly and the real problem is in pciehp.

That's why I've been trying to have a conversation about how we
interpret the spec and how we could remove PM and pciehp from the
picture and experiment directly with setpci.

[1] https://lkml.kernel.org/r/1481317564-18045-1-git-send-email-ashok.raj@intel.com
[2] https://bugzilla.kernel.org/show_bug.cgi?id=117561