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Message-ID: <20170210085028.GA6570@gmail.com>
Date: Fri, 10 Feb 2017 09:50:28 +0100
From: Ingo Molnar <mingo@...nel.org>
To: kan.liang@...el.com
Cc: peterz@...radead.org, linux-kernel@...r.kernel.org,
eranian@...gle.com, ak@...ux.intel.com
Subject: Re: [PATCH] x86, perf: Add Top Down events to Intel Goldmont
* kan.liang@...el.com <kan.liang@...el.com> wrote:
> From: Kan Liang <kan.liang@...el.com>
>
> Goldmont supports full Top Down level 1 metrics (FrontendBound,
> Retiring, Backend Bound and Bad Speculation).
> It has 3 wide pipeline.
>
> Signed-off-by: Kan Liang <kan.liang@...el.com>
> ---
> arch/x86/events/intel/core.c | 26 ++++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index eb1484c..baaac28 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -1553,6 +1553,31 @@ static __initconst const u64 slm_hw_cache_event_ids
> },
> };
>
> +EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
> +EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
> +/* UOPS_NOT_DELIVERED.ANY */
> +EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm,
> + "event=0x9c");
> +/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
> +EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm,
> + "event=0xca,umask=0x02");
> +/* UOPS_RETIRED.ANY */
> +EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm,
> + "event=0xc2");
> +/* UOPS_ISSUED.ANY */
> +EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm,
> + "event=0x0e");
Please don't
break lines
in funny places and make code
unreadable.
Instead have a look at the existing event listing style in
arch/x86/events/intel/core.c and match that!
Ok?
Thanks,
Ingo
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