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Message-ID: <20170214123149.GV6515@twins.programming.kicks-ass.net>
Date: Tue, 14 Feb 2017 13:31:49 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
Cc: linux-kernel@...r.kernel.org, iommu@...ts.linux-foundation.org,
joro@...tes.org, bp@...en8.de, mingo@...hat.com
Subject: Re: [PATCH v8 9/9] perf/amd/iommu: Enable support for multiple IOMMUs
On Tue, Feb 07, 2017 at 08:57:52AM +0700, Suravee Suthikulpanit wrote:
> >But instead it looks like you get the counter form:
> >
> > #define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg))
> >
> >Which is absolutely insane.
> >
>
> So, the IOMMU counters are grouped into bank, and there could be
> many banks. I use the extra_reg.reg to hold the bank and counter
> indices. This will be used to program onto the counter configuration
> register. This is handled in get_next_avail_iommu_bnk_cntr() and
> clear_avail_iommu_bnk_cntr().
But this is crazy. That's not what extra_regs are for. Also, who cares
about the banks, why is this exposed?
That is, I would very much expect a linear range of counters. You can
always decompose this counter number if you really need to somewhere
down near the hardware accessors.
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