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Date:   Mon, 20 Feb 2017 11:09:43 +0000
From:   Mark Rutland <mark.rutland@....com>
To:     Anurup M <anurupvasu@...il.com>
Cc:     will.deacon@....com, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, anurup.m@...wei.com,
        zhangshaokun@...ilicon.com, tanxiaojun@...wei.com,
        xuwei5@...ilicon.com, sanil.kumar@...ilicon.com,
        john.garry@...wei.com, gabriele.paoloni@...wei.com,
        shiju.jose@...wei.com, huangdaode@...ilicon.com,
        linuxarm@...wei.com, dikshit.n@...wei.com, shyju.pv@...wei.com
Subject: Re: [PATCH v4 08/11] drivers: perf: hisi: use poll method to avoid
 L3C counter overflow

On Sun, Feb 19, 2017 at 01:51:03PM -0500, Anurup M wrote:
> The L3 cache PMU use N-N SPI interrupt which has no support
> in kernel mainline.

Could you elaborate on what you mean by this?

I don't understand what is meant here. How exactly are the interrupts
wired up in HW, and what exactly is not supported by Linux?

> So use hrtimer to poll and update event
> counter to avoid overflow condition for L3 cache PMU.
> A interval of 10 seconds is used for the hrtimer.
> The time interval can be configured in the sysfs.

I'm not too keen on giving userspace the ability to control this, since
it gives an awful lot of rope for userspace to tie around itself.

Thanks,
Mark.

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