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Date: Mon, 20 Feb 2017 08:39:18 +0530
From: Hemant Kumar <hemant@...ux.vnet.ibm.com>
To: linuxppc-dev@...ts.ozlabs.org
Cc: linux-kernel@...r.kernel.org,
Hemant Kumar <hemant@...ux.vnet.ibm.com>,
Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>,
Michael Ellerman <mpe@...erman.id.au>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
Paul Mackerras <paulus@...ba.org>,
Anton Blanchard <anton@...ba.org>,
Sukadev Bhattiprolu <sukadev@...ux.vnet.ibm.com>,
Michael Neuling <mikey@...ling.org>,
Stewart Smith <stewart@...ux.vnet.ibm.com>,
Daniel Axtens <dja@...ens.net>,
Stephane Eranian <eranian@...gle.com>,
Balbir Singh <bsingharora@...il.com>,
Anju T Sudhakar <anju@...ux.vnet.ibm.com>
Subject: [PATCH v4 01/10] powerpc/powernv: Data structure and macros definitions
Create new header file "imc-pmu.h" to add the data structures
and macros needed for IMC pmu support.
Cc: Madhavan Srinivasan <maddy@...ux.vnet.ibm.com>
Cc: Michael Ellerman <mpe@...erman.id.au>
Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc: Paul Mackerras <paulus@...ba.org>
Cc: Anton Blanchard <anton@...ba.org>
Cc: Sukadev Bhattiprolu <sukadev@...ux.vnet.ibm.com>
Cc: Michael Neuling <mikey@...ling.org>
Cc: Stewart Smith <stewart@...ux.vnet.ibm.com>
Cc: Daniel Axtens <dja@...ens.net>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Balbir Singh <bsingharora@...il.com>
Cc: Anju T Sudhakar <anju@...ux.vnet.ibm.com>
Signed-off-by: Hemant Kumar <hemant@...ux.vnet.ibm.com>
---
arch/powerpc/include/asm/imc-pmu.h | 73 ++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
create mode 100644 arch/powerpc/include/asm/imc-pmu.h
diff --git a/arch/powerpc/include/asm/imc-pmu.h b/arch/powerpc/include/asm/imc-pmu.h
new file mode 100644
index 0000000..3232322
--- /dev/null
+++ b/arch/powerpc/include/asm/imc-pmu.h
@@ -0,0 +1,73 @@
+#ifndef PPC_POWERNV_IMC_PMU_DEF_H
+#define PPC_POWERNV_IMC_PMU_DEF_H
+
+/*
+ * IMC Nest Performance Monitor counter support.
+ *
+ * Copyright (C) 2016 Madhavan Srinivasan, IBM Corporation.
+ * (C) 2016 Hemant K Shaw, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/perf_event.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <asm/opal.h>
+
+#define IMC_MAX_CHIPS 32
+#define IMC_MAX_PMUS 32
+#define IMC_MAX_PMU_NAME_LEN 256
+
+#define NEST_IMC_ENGINE_START 1
+#define NEST_IMC_ENGINE_STOP 0
+#define NEST_MAX_PAGES 16
+
+#define NEST_IMC_PRODUCTION_MODE 1
+
+#define IMC_DTB_COMPAT "ibm,opal-in-memory-counters"
+#define IMC_DTB_NEST_COMPAT "ibm,imc-counters-nest"
+
+/*
+ * Structure to hold per chip specific memory address
+ * information for nest pmus. Nest Counter data are exported
+ * in per-chip reserved memory region by the PORE Engine.
+ */
+struct perchip_nest_info {
+ u32 chip_id;
+ u64 pbase;
+ u64 vbase[NEST_MAX_PAGES];
+ u64 size;
+};
+
+/*
+ * Place holder for nest pmu events and values.
+ */
+struct imc_events {
+ char *ev_name;
+ char *ev_value;
+};
+
+/*
+ * Device tree parser code detects IMC pmu support and
+ * registers new IMC pmus. This structure will
+ * hold the pmu functions and attrs for each imc pmu and
+ * will be referenced at the time of pmu registration.
+ */
+struct imc_pmu {
+ struct pmu pmu;
+ int domain;
+ const struct attribute_group *attr_groups[4];
+};
+
+/*
+ * Domains for IMC PMUs
+ */
+#define IMC_DOMAIN_NEST 1
+
+#define UNKNOWN_DOMAIN -1
+
+#endif /* PPC_POWERNV_IMC_PMU_DEF_H */
--
2.7.4
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