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Date:   Wed, 22 Feb 2017 12:34:56 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...entembedded.com>
To:     Chunfeng Yun <chunfeng.yun@...iatek.com>,
        Kishon Vijay Abraham I <kishon@...com>
Cc:     Matthias Brugger <matthias.bgg@...il.com>,
        Felipe Balbi <felipe.balbi@...ux.intel.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Ian Campbell <ijc+devicetree@...lion.org.uk>,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-usb@...r.kernel.org, linux-mediatek@...ts.infradead.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v3 4/8] phy: phy-mt65xx-usb3: move clock from phy node
 into port nodes

Hello!

On 2/22/2017 11:55 AM, Chunfeng Yun wrote:

> the reference clock of HighSpeed port is 48M which comes from PLL;
> the reference clock of SuperSpeed port is 26M which usually comes
> from 26M oscillator directly, but some SoCs are not, add it for

     ... but on some SoCs does not?

> compatibility, and put them into port node for flexibility.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@...iatek.com>
[...]

MBR, Sergei

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