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Message-ID: <1487776444-4701-1-git-send-email-pdeschrijver@nvidia.com>
Date: Wed, 22 Feb 2017 17:13:55 +0200
From: Peter De Schrijver <pdeschrijver@...dia.com>
To: Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Michael Turquette <mturquette@...libre.com>,
"Stephen Boyd" <sboyd@...eaurora.org>,
Stephen Warren <swarren@...dotorg.org>,
"Thierry Reding" <thierry.reding@...il.com>,
Alexandre Courbot <gnurou@...il.com>,
"Rob Herring" <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
"Rhyland Klein" <rklein@...dia.com>, <linux-clk@...r.kernel.org>,
<linux-tegra@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>
Subject: [PATCH 0/7] Tegra210 clock bug fixes
A number of bug fixes for the Tegra210 clock implementation.
Peter De Schrijver (7):
clk: tegra: fix pll_a1 iddq register, add pll_a1
clk: tegra: fix isp clock modelling
clk: tegra: correct afi parent
clk: tegra: remove non-existing pll_m_out1 clock
clk: tegra: don't warn for PLL defaults unnecessarily
clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation
clk: tegra: fix type for m field
drivers/clk/tegra/clk-id.h | 1 +
drivers/clk/tegra/clk-tegra-periph.c | 13 +++++++++---
drivers/clk/tegra/clk-tegra210.c | 35 ++++++++++++++++++++------------
drivers/clk/tegra/clk.h | 2 +-
include/dt-bindings/clock/tegra210-car.h | 4 ++--
5 files changed, 36 insertions(+), 19 deletions(-)
--
1.9.1
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