linux-kernel - Re: [PATCH 1/7] clk: tegra: fix pll_a1 iddq register, add pll

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <67a5d147-b6ed-256b-a269-29456043a20c@kapsi.fi>
Date:   Wed, 22 Feb 2017 18:38:52 +0200
From:   Mikko Perttunen <cyndis@...si.fi>
To:     Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Stephen Warren <swarren@...dotorg.org>,
        Thierry Reding <thierry.reding@...il.com>,
        Alexandre Courbot <gnurou@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Rhyland Klein <rklein@...dia.com>, linux-clk@...r.kernel.org,
        linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 1/7] clk: tegra: fix pll_a1 iddq register, add pll_a1

Reviewed-by: Mikko Perttunen <mperttunen@...dia.com>

On 02/22/2017 05:13 PM, Peter De Schrijver wrote:
> pll_a1 was using CLK_RST_CONTROLLER_PLLA1_MISC_0 for IDDQ control rather
> than the correct register CLK_RST_CONTROLLER_PLLA1_MISC_1. Also add pll_a1
> to the set of clocks defined for Tegra210.
>
> Signed-off-by: Peter De Schrijver <pdeschrijver@...dia.com>
> ---
>  drivers/clk/tegra/clk-tegra210.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
> index 2896d2e..2ef8d49 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -1772,7 +1772,7 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
>  	.misc_reg = PLLA1_MISC0,
>  	.lock_mask = PLLCX_BASE_LOCK,
>  	.lock_delay = 300,
> -	.iddq_reg = PLLA1_MISC0,
> +	.iddq_reg = PLLA1_MISC1,
>  	.iddq_bit_idx = PLLCX_IDDQ_BIT,
>  	.reset_reg = PLLA1_MISC0,
>  	.reset_bit_idx = PLLCX_RESET_BIT,
> @@ -2209,6 +2209,7 @@ static u32 pll_expo_p_to_pdiv(u32 p, u32 *pdiv)
>  	[tegra_clk_pll_c4_out2] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT2, .present = true },
>  	[tegra_clk_pll_c4_out3] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT3, .present = true },
>  	[tegra_clk_apb2ape] = { .dt_id = TEGRA210_CLK_APB2APE, .present = true },
> +	[tegra_clk_pll_a1] = { .dt_id = TEGRA210_CLK_PLL_A1, .present = true },
>  };
>
>  static struct tegra_devclk devclks[] __initdata = {
>