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Date:   Wed, 22 Feb 2017 09:45:01 -0800
From:   David Daney <ddaney.cavm@...il.com>
To:     Christoph Hellwig <hch@....de>,
        David Daney <ddaney@...iumnetworks.com>
Cc:     George Cherian <gcherian@...iumnetworks.com>,
        George Cherian <george.cherian@...ium.com>,
        David Daney <david.daney@...ium.com>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        linux-crypto@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: crypto/cavium MSI-X fixups

On 02/21/2017 11:27 PM, Christoph Hellwig wrote:
> On Tue, Feb 21, 2017 at 09:36:04AM -0800, David Daney wrote:
>> With respect to pci_enable_msix(), what do you recommend as a replacement?
>
> pci_alloc_irq_vectors.  In fact I have a tree ready for after -rc1
> that removes pci_enable_msix() entirely.

I would like to see something that handles the case of this driver that 
I am attempting to get merged:


https://lkml.org/lkml/2017/2/15/1209


>
>> For the crypto/cavium driver, you recommend pci_alloc_irq_vectors(), which
>> works well if the required MSI-X indexes are contiguous starting at zero.
>> What would be used for a device that has 184 MSI-X, but only a sparse
>> subset (fewer than half) of these are required for the driver operation.
>> It would waste system resources to use an API that forces us to allocate
>> 184 when only 80 are required.
>
> Currently we don't have a good API for that.  I've not been through all
> users of pci_enable_msix_{range,exact} yet, but so far I've only found
> one user not using all vectors from 0 to some limit.  Depending how many
> such users we have and how they'll look I will have to look into an API
> to support that use case.
>

See the patch above for the case that doesn't use 0..UPPER_LIMIT

David Daney

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