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Date:   Wed, 22 Feb 2017 11:18:48 -0800
From:   Andi Kleen <>
To:     "Liang, Kan" <>
Cc:     Vince Weaver <>,
        Peter Zijlstra <>,
        "Odzioba, Lukasz" <>,
        Stephane Eranian <>,
        "" <>,
        LKML <>,
        Alexander Shishkin <>
Subject: Re: [PATCH] perf/x86: fix event counter update issue

> No. It related to the counter width. The number of bits we can use should be
> 1 bit less than the total width. Otherwise, there will be problem.
> For big cores such as haswell, broadwell, skylake, the counter width is 48 bit.
> So we can only use 47 bits.
> For Silvermont and KNL, the counter width is only 32 bit I think. So we can only
> use 31 bits.

It is 40 bits on these cores, so 39bits.


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