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Message-ID: <20170223141721.6o4r5c636onwnlme@pd.tnic>
Date:   Thu, 23 Feb 2017 15:17:21 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     Josh Poimboeuf <jpoimboe@...hat.com>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...nel.org>,
        "H. Peter Anvin" <hpa@...or.com>, linux-kernel@...r.kernel.org,
        torvalds@...ux-foundation.org, arjan@...ux.intel.com,
        richard.weinberger@...il.com
Subject: Re: [PATCH] x86: Implement __WARN using UD0

On Thu, Feb 23, 2017 at 08:12:32AM -0600, Josh Poimboeuf wrote:
> I guess AMD64 and hypervisors don't need to know about it, since if they

So the insns are mentioned in AMD's APMv2, in the instruction tables at
the end. Just not fully documented like UD2.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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