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Message-ID: <e4c8c705-80a3-e345-7020-85fca0aba6d8@oracle.com>
Date: Thu, 23 Feb 2017 13:53:01 -0800
From: yinghai.lu@...cle.com
To: James Puthukattukaran <james.puthukattukaran@...cle.com>,
Yinghai Lu <yinghai@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Ashok Raj <ashok.raj@...el.com>, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] PCI,pciehp: Move printout before write_cmd
yes.
On 02/23/2017 01:55 PM, James Puthukattukaran wrote:
> So, the issue is that you could get the following sequence -
>
> write command
> print out in ISR for pending interrupt
> ctrl_dbg message for write command
>
> and this makes it look like the write command occurred after the
> pending interrupt message?
>
>
>
> On 02/23/2017 03:28 PM, Yinghai Lu wrote:
>> Bjorn complained some strange print out for pending interrupts.
>>
>> Actually that is caused that have cmd print out after write_cmd.
>>
>> Adjust the sequence to get right order for debug print out.
>>
>> Signed-off-by: Yinghai Lu <yinghai@...nel.org>
>>
>> diff --git a/drivers/pci/hotplug/pciehp_hpc.c
>> b/drivers/pci/hotplug/pciehp_hpc.c
>> index 026830a..94df18f99 100644
>> --- a/drivers/pci/hotplug/pciehp_hpc.c
>> +++ b/drivers/pci/hotplug/pciehp_hpc.c
>> @@ -475,9 +475,9 @@ void pciehp_set_attention_status(struct slot
>> *slot, u8 value)
>> default:
>> return;
>> }
>> - pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, slot_cmd);
>> + pcie_write_cmd_nowait(ctrl, slot_cmd, PCI_EXP_SLTCTL_AIC);
>> }
>> void pciehp_green_led_on(struct slot *slot)
>> @@ -487,11 +487,11 @@ void pciehp_green_led_on(struct slot *slot)
>> if (!PWR_LED(ctrl))
>> return;
>> - pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
>> - PCI_EXP_SLTCTL_PIC);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
>> PCI_EXP_SLTCTL_PWR_IND_ON);
>> + pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_ON,
>> + PCI_EXP_SLTCTL_PIC);
>> }
>> void pciehp_green_led_off(struct slot *slot)
>> @@ -501,11 +501,11 @@ void pciehp_green_led_off(struct slot *slot)
>> if (!PWR_LED(ctrl))
>> return;
>> - pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
>> - PCI_EXP_SLTCTL_PIC);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
>> PCI_EXP_SLTCTL_PWR_IND_OFF);
>> + pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_OFF,
>> + PCI_EXP_SLTCTL_PIC);
>> }
>> void pciehp_green_led_blink(struct slot *slot)
>> @@ -515,11 +515,11 @@ void pciehp_green_led_blink(struct slot *slot)
>> if (!PWR_LED(ctrl))
>> return;
>> - pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
>> - PCI_EXP_SLTCTL_PIC);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
>> PCI_EXP_SLTCTL_PWR_IND_BLINK);
>> + pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_PWR_IND_BLINK,
>> + PCI_EXP_SLTCTL_PIC);
>> }
>> int pciehp_power_on_slot(struct slot *slot)
>> @@ -536,10 +536,10 @@ int pciehp_power_on_slot(struct slot *slot)
>> PCI_EXP_SLTSTA_PFD);
>> ctrl->power_fault_detected = 0;
>> - pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
>> PCI_EXP_SLTCTL_PWR_ON);
>> + pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_ON, PCI_EXP_SLTCTL_PCC);
>> retval = pciehp_link_enable(ctrl);
>> if (retval)
>> @@ -552,10 +552,10 @@ void pciehp_power_off_slot(struct slot *slot)
>> {
>> struct controller *ctrl = slot->ctrl;
>> - pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL,
>> PCI_EXP_SLTCTL_PWR_OFF);
>> + pcie_write_cmd(ctrl, PCI_EXP_SLTCTL_PWR_OFF, PCI_EXP_SLTCTL_PCC);
>> }
>> static irqreturn_t pciehp_isr(int irq, void *dev_id)
>> @@ -701,9 +701,9 @@ void pcie_enable_notification(struct controller
>> *ctrl)
>> PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
>> PCI_EXP_SLTCTL_DLLSCE);
>> - pcie_write_cmd_nowait(ctrl, cmd, mask);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd);
>> + pcie_write_cmd_nowait(ctrl, cmd, mask);
>> }
>> static void pcie_disable_notification(struct controller *ctrl)
>> @@ -714,9 +714,9 @@ static void pcie_disable_notification(struct
>> controller *ctrl)
>> PCI_EXP_SLTCTL_MRLSCE | PCI_EXP_SLTCTL_PFDE |
>> PCI_EXP_SLTCTL_HPIE | PCI_EXP_SLTCTL_CCIE |
>> PCI_EXP_SLTCTL_DLLSCE);
>> - pcie_write_cmd(ctrl, 0, mask);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
>> + pcie_write_cmd(ctrl, 0, mask);
>> }
>> /*
>> @@ -743,18 +743,18 @@ int pciehp_reset_slot(struct slot *slot, int
>> probe)
>> ctrl_mask |= PCI_EXP_SLTCTL_DLLSCE;
>> stat_mask |= PCI_EXP_SLTSTA_DLLSC;
>> - pcie_write_cmd(ctrl, 0, ctrl_mask);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, 0);
>> + pcie_write_cmd(ctrl, 0, ctrl_mask);
>> if (pciehp_poll_mode)
>> del_timer_sync(&ctrl->poll_timer);
>> pci_reset_bridge_secondary_bus(ctrl->pcie->port);
>> pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, stat_mask);
>> - pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
>> ctrl_dbg(ctrl, "%s: SLOTCTRL %x write cmd %x\n", __func__,
>> pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, ctrl_mask);
>> + pcie_write_cmd_nowait(ctrl, ctrl_mask, ctrl_mask);
>> if (pciehp_poll_mode)
>> int_poll_timeout(ctrl->poll_timer.data);
>
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