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Date:   Tue, 28 Feb 2017 17:19:50 +0200
From:   Peter De Schrijver <pdeschrijver@...dia.com>
To:     Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen Boyd" <sboyd@...eaurora.org>,
        Stephen Warren <swarren@...dotorg.org>,
        "Thierry Reding" <thierry.reding@...il.com>,
        Alexandre Courbot <gnurou@...il.com>,
        <linux-clk@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on

This is needed to make the JTAG debugging interface work.

Signed-off-by: Peter De Schrijver <pdeschrijver@...dia.com>
---
 drivers/clk/tegra/clk-tegra210.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 9a2512a..708f5f1 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -2680,6 +2680,7 @@ static void tegra210_cpu_clock_resume(void)
 	{ TEGRA210_CLK_EMC, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA210_CLK_MSELECT, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA210_CLK_CSITE, TEGRA210_CLK_CLK_MAX, 0, 1 },
+	{ TEGRA210_CLK_DBGAPB, TEGRA210_CLK_CLK_MAX, 0, 1 },
 	{ TEGRA210_CLK_TSENSOR, TEGRA210_CLK_CLK_M, 400000, 0 },
 	{ TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
 	{ TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
-- 
1.9.1

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