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Message-Id: <98af74599ea0757098a5776ea29e581b661dcf6f.1488345270.git.len.brown@intel.com>
Date:   Wed,  1 Mar 2017 00:27:22 -0500
From:   Len Brown <lenb@...nel.org>
To:     linux-pm@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, Len Brown <len.brown@...el.com>,
        x86@...nel.org
Subject: [PATCH 18/44] x86 msr_index.h: Define MSR_MISC_FEATURE_CONTROL

From: Len Brown <len.brown@...el.com>

This non-architectural MSR has disable bits
for various prefetchers on modern processors.

While these bits are generally touched only by the BIOS,
say, via BIOS SETUP, it is useful to dump them
when examining options that can alter performance.

Cc: x86@...nel.org
Signed-off-by: Len Brown <len.brown@...el.com>
---
 arch/x86/include/asm/msr-index.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 83bc672c225c..312fb7e14cdd 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -467,6 +467,7 @@
 
 #define MSR_IA32_TEMPERATURE_TARGET	0x000001a2
 
+#define MSR_MISC_FEATURE_CONTROL	0x000001a4
 #define MSR_MISC_PWR_MGMT		0x000001aa
 
 #define MSR_IA32_ENERGY_PERF_BIAS	0x000001b0
-- 
2.11.0.161.g6610af872

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