linux-kernel - Re: [PATCH 5/9] dmaengine: sun6i: support V3s SoC variant

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Date:   Wed, 1 Mar 2017 10:32:52 +0100
From:   Maxime Ripard <maxime.ripard@...e-electrons.com>
To:     Icenowy Zheng <icenowy@...c.xyz>
Cc:     Vinod Koul <vinod.koul@...el.com>,
        Rob Herring <robh+dt@...nel.org>, Chen-Yu Tsai <wens@...e.org>,
        Mark Brown <broonie@...nel.org>,
        "dmaengine@...r.kernel.org" <dmaengine@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
Subject: Re: [PATCH 5/9] dmaengine: sun6i: support V3s SoC variant

On Wed, Mar 01, 2017 at 01:58:33AM +0800, Icenowy Zheng wrote:
> 
> 
> 01.03.2017, 01:56, "Maxime Ripard" <maxime.ripard@...e-electrons.com>:
> > On Mon, Feb 27, 2017 at 06:48:01PM +0800, Icenowy Zheng wrote:
> >>  27.02.2017, 15:50, "Maxime Ripard" <maxime.ripard@...e-electrons.com>:
> >>  > On Sat, Feb 25, 2017 at 08:30:25PM +0800, Icenowy Zheng wrote:
> >>  >>  Allwinner V3s has a DMA engine similar to the ones from A31, but with
> >>  >>  fewer channels and DRQs.
> >>  >>
> >>  >>  Add support for it.
> >>  >>
> >>  >>  As it also needs the special gate bit, make the gate bit generic.
> >>  >
> >>  > That should be part of a separate patch.
> >>
> >>  OK.
> >>
> >>  >
> >>  >>  According to BSP source code, SUN8IW6 (A83T) also needs the bit, so it
> >>  >>  have also been specified gate_needed property.
> >>  >>
> >>  >>  Signed-off-by: Icenowy Zheng <icenowy@...c.xyz>
> >>  >>  ---
> >>  >>   Documentation/devicetree/bindings/dma/sun6i-dma.txt | 1 +
> >>  >>   drivers/dma/sun6i-dma.c | 17 ++++++++++++++---
> >>  >>   2 files changed, 15 insertions(+), 3 deletions(-)
> >>  >>
> >>  >>  diff --git a/Documentation/devicetree/bindings/dma/sun6i-dma.txt b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
> >>  >>  index 6b267045f522..98fbe1a5c6dd 100644
> >>  >>  --- a/Documentation/devicetree/bindings/dma/sun6i-dma.txt
> >>  >>  +++ b/Documentation/devicetree/bindings/dma/sun6i-dma.txt
> >>  >>  @@ -9,6 +9,7 @@ Required properties:
> >>  >>                     "allwinner,sun8i-a23-dma"
> >>  >>                     "allwinner,sun8i-a83t-dma"
> >>  >>                     "allwinner,sun8i-h3-dma"
> >>  >>  + "allwinner,sun8i-v3s-dma"
> >>  >>   - reg: Should contain the registers base address and length
> >>  >>   - interrupts: Should contain a reference to the interrupt used by this device
> >>  >>   - clocks: Should contain a reference to the parent AHB clock
> >>  >>  diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> >>  >>  index a2358780ab2c..1f38424c1b14 100644
> >>  >>  --- a/drivers/dma/sun6i-dma.c
> >>  >>  +++ b/drivers/dma/sun6i-dma.c
> >>  >>  @@ -101,6 +101,7 @@ struct sun6i_dma_config {
> >>  >>           u32 nr_max_channels;
> >>  >>           u32 nr_max_requests;
> >>  >>           u32 nr_max_vchans;
> >>  >>  + bool gate_needed;
> >>  >>   };
> >>  >>
> >>  >>   /*
> >>  >>  @@ -1009,12 +1010,14 @@ static struct sun6i_dma_config sun8i_a23_dma_cfg = {
> >>  >>           .nr_max_channels = 8,
> >>  >>           .nr_max_requests = 24,
> >>  >>           .nr_max_vchans = 37,
> >>  >>  + .gate_needed = true,
> >>  >>   };
> >>  >>
> >>  >>   static struct sun6i_dma_config sun8i_a83t_dma_cfg = {
> >>  >>           .nr_max_channels = 8,
> >>  >>           .nr_max_requests = 28,
> >>  >>           .nr_max_vchans = 39,
> >>  >>  + .gate_needed = true,
> >>  >>   };
> >>  >>
> >>  >>   /*
> >>  >>  @@ -1028,11 +1031,19 @@ static struct sun6i_dma_config sun8i_h3_dma_cfg = {
> >>  >>           .nr_max_vchans = 34,
> >>  >>   };
> >>  >>
> >>  >>  +static struct sun6i_dma_config sun8i_v3s_dma_cfg = {
> >>  >>  + .nr_max_channels = 8,
> >>  >>  + .nr_max_requests = 23,
> >>  >>  + .nr_max_vchans = 24,
> >>  >
> >>  > This one is suspicious. There's just a single endpoint that can be
> >>  > used in both directions?
> >>
> >>  nr_max_vchans is the endpoint number. nr_max_requests is the
> >>  maximum DRQ number, for V3s, according to the datasheet, it's
> >>  23: SPI0_{R,T}X.
> >
> > There's not a lot of endpoints indeed, but you need 28 vchans (2 *
> > 14).
> 
> Sorry but I counted only 12 pairs of vchans:
> Port 0. SRAM
> Port 1. SDRAM
> Port 6. UART0
> Port 7. UART1
> Port 8. UART2
> Port 15. Audio Codec
> Port 16. CE
> Port 17. OTG EP1
> Port 18. OTG EP2
> Port 19. OTG EP3
> Port 20. OTG EP4
> Port 23. SPI0

It seems like I can't count anymore... Yes, you're right, sorry.

Having a comment on top of the structure, just like all the other SoCs
would be nice though.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

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