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Message-ID: <090d9947-8003-4608-5e3a-92f62f90eda6@synopsys.com>
Date: Tue, 7 Mar 2017 11:18:35 +0000
From: Joao Pinto <Joao.Pinto@...opsys.com>
To: Kishon Vijay Abraham I <kishon@...com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Joao Pinto <Joao.Pinto@...opsys.com>,
<linux-pci@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-omap@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-samsung-soc@...r.kernel.org>, <linux-arm-kernel@...s.com>
CC: <nsekhar@...com>, Jingoo Han <jingoohan1@...il.com>,
Richard Zhu <hongxing.zhu@....com>,
Lucas Stach <l.stach@...gutronix.de>,
"Murali Karicheri" <m-karicheri2@...com>,
Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
Niklas Cassel <niklas.cassel@...s.com>,
Jesper Nilsson <jesper.nilsson@...s.com>,
Zhou Wang <wangzhou1@...ilicon.com>,
Gabriele Paoloni <gabriele.paoloni@...wei.com>
Subject: Re: [PATCH v2 5/7] PCI: dwc: all: Modify dbi accessors to access data
of 4/2/1 bytes
Às 9:52 AM de 3/7/2017, Kishon Vijay Abraham I escreveu:
> Previously dbi accessors can be used to access data of size 4
> bytes. But there might be situations (like accessing
> MSI_MESSAGE_CONTROL in order to set/get the number of required
> MSI interrupts in EP mode) where dbi accessors must
> be used to access data of size 2. This is in preparation for
> adding endpoint mode support to designware driver.
>
> Cc: Jingoo Han <jingoohan1@...il.com>
> Cc: Richard Zhu <hongxing.zhu@....com>
> Cc: Lucas Stach <l.stach@...gutronix.de>
> Cc: Murali Karicheri <m-karicheri2@...com>
> Cc: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
> Cc: Niklas Cassel <niklas.cassel@...s.com>
> Cc: Jesper Nilsson <jesper.nilsson@...s.com>
> Cc: Joao Pinto <Joao.Pinto@...opsys.com>
> Cc: Zhou Wang <wangzhou1@...ilicon.com>
> Cc: Gabriele Paoloni <gabriele.paoloni@...wei.com>
> Signed-off-by: Kishon Vijay Abraham I <kishon@...com>
> ---
> drivers/pci/dwc/Kconfig | 18 ++++----
> drivers/pci/dwc/pci-dra7xx.c | 8 ++--
> drivers/pci/dwc/pci-exynos.c | 16 +++----
> drivers/pci/dwc/pci-imx6.c | 54 +++++++++++-----------
> drivers/pci/dwc/pci-keystone-dw.c | 13 +++---
> drivers/pci/dwc/pcie-armada8k.c | 38 ++++++++--------
> drivers/pci/dwc/pcie-artpec6.c | 6 +--
> drivers/pci/dwc/pcie-designware-host.c | 18 ++++----
> drivers/pci/dwc/pcie-designware.c | 77 +++++++++++++++++++-------------
> drivers/pci/dwc/pcie-designware.h | 14 +++---
> drivers/pci/dwc/pcie-hisi.c | 14 +++---
> 11 files changed, 147 insertions(+), 129 deletions(-)
>
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..cb3d5d0 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -36,7 +36,7 @@ config PCIE_DW_PLAT
> config PCI_EXYNOS
> bool "Samsung Exynos PCIe controller"
> depends on PCI
> - depends on SOC_EXYNOS5440
> + depends on SOC_EXYNOS5440 || COMPILE_TEST
Kishon, I have the idea that Bjorn suggested some time ago not to use
COMPILE_TEST, because there were some problems in some drivers that needed
specific arch stuff.
Bjorn: Could you please confirm?
Thanks.
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