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Date: Tue, 7 Mar 2017 11:12:33 +0000
From: Vladimir Murzin <vladimir.murzin@....com>
To: linux-arm-kernel@...ts.infradead.org
Cc: kbuild-all@...org, linux-kernel@...r.kernel.org,
linux@...linux.org.uk, akpm@...ux-foundation.org,
robin.murphy@....com, benjamin.gaignard@...aro.org,
alexandre.torgue@...com, sza@....hu
Subject: [PATCH v2 6/7] ARM: NOMMU: Set ARM_DMA_MEM_BUFFERABLE for M-class cpus
Now, we have dedicated non-cacheable region for consistent DMA
operations. However, that region can still be marked as bufferable by
MPU, so it'd be safer to have barriers by default.
Tested-by: Benjamin Gaignard <benjamin.gaignard@...aro.org>
Tested-by: Andras Szemzo <sza@....hu>
Tested-by: Alexandre TORGUE <alexandre.torgue@...com>
Reviewed-by: Robin Murphy <robin.murphy@....com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@....com>
---
arch/arm/mm/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index d731f28..7dd46ae 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -1050,7 +1050,7 @@ config ARM_L1_CACHE_SHIFT
config ARM_DMA_MEM_BUFFERABLE
bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
- default y if CPU_V6 || CPU_V6K || CPU_V7
+ default y if CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M
help
Historically, the kernel has used strongly ordered mappings to
provide DMA coherent memory. With the advent of ARMv7, mapping
--
2.0.0
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