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Message-ID: <aa9835a7-07f4-d042-d04a-b0d9cc0ea3de@synopsys.com>
Date: Wed, 8 Mar 2017 11:32:58 +0000
From: Joao Pinto <Joao.Pinto@...opsys.com>
To: Kishon Vijay Abraham I <kishon@...com>,
Joao Pinto <Joao.Pinto@...opsys.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
Jingoo Han <jingoohan1@...il.com>
CC: <linux-pci@...r.kernel.org>, <linux-doc@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-omap@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <nsekhar@...com>
Subject: Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support
Hi Kishon,
>> Can you provide PCIE_GET_ATU_INB_UNR_REG_OFFSET (similar to
>> PCIE_GET_ATU_OUTB_UNR_REG_OFFSET)?
>
> Yes of course, I will send you the definition soon.
As promissed here is the definition for Inbound:
+/* register address builder */
+#define PCIE_GET_ATU_INB_UNR_REG_ADDR(region, register) \
+ ((0x3 << 20) | (region << 9) | \
+ (0x1 << 8) | (register << 2))
Thanks,
Joao
>
> Thanks,
> Joao
>
>>
>> Thanks
>> Kishon
>>
>
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