linux-kernel - RE: [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont

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Date:   Wed, 8 Mar 2017 15:17:44 +0000
From:   "Liang, Kan" <kan.liang@...el.com>
To:     "peterz@...radead.org" <peterz@...radead.org>,
        "mingo@...nel.org" <mingo@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "eranian@...gle.com" <eranian@...gle.com>,
        "ak@...ux.intel.com" <ak@...ux.intel.com>
Subject: RE: [PATCH V2] x86, perf: Add Top Down events to Intel Goldmont


Ping.
Any comments for this patch?

Thanks,
Kan

> 
> From: Kan Liang <kan.liang@...el.com>
> 
> Goldmont supports full Top Down level 1 metrics (FrontendBound,
> Retiring, Backend Bound and Bad Speculation).
> It has 3 wide pipeline.
> 
> Signed-off-by: Kan Liang <kan.liang@...el.com>
> ---
> 
> Changes since V1:
>  - Change event list style
> 
>  arch/x86/events/intel/core.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index eb1484c..4244bed 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -1553,6 +1553,27 @@ static __initconst const u64
> slm_hw_cache_event_ids
>   },
>  };
> 
> +EVENT_ATTR_STR(topdown-total-slots, td_total_slots_glm, "event=0x3c");
> +EVENT_ATTR_STR(topdown-total-slots.scale, td_total_slots_scale_glm, "3");
> +/* UOPS_NOT_DELIVERED.ANY */
> +EVENT_ATTR_STR(topdown-fetch-bubbles, td_fetch_bubbles_glm,
> "event=0x9c");
> +/* ISSUE_SLOTS_NOT_CONSUMED.RECOVERY */
> +EVENT_ATTR_STR(topdown-recovery-bubbles, td_recovery_bubbles_glm,
> "event=0xca,umask=0x02");
> +/* UOPS_RETIRED.ANY */
> +EVENT_ATTR_STR(topdown-slots-retired, td_slots_retired_glm,
> "event=0xc2");
> +/* UOPS_ISSUED.ANY */
> +EVENT_ATTR_STR(topdown-slots-issued, td_slots_issued_glm,
> "event=0x0e");
> +
> +static struct attribute *glm_events_attrs[] = {
> +	EVENT_PTR(td_total_slots_glm),
> +	EVENT_PTR(td_total_slots_scale_glm),
> +	EVENT_PTR(td_fetch_bubbles_glm),
> +	EVENT_PTR(td_recovery_bubbles_glm),
> +	EVENT_PTR(td_slots_issued_glm),
> +	EVENT_PTR(td_slots_retired_glm),
> +	NULL
> +};
> +
>  static struct extra_reg intel_glm_extra_regs[] __read_mostly = {
>  	/* must define OFFCORE_RSP_X first, see intel_fixup_er() */
>  	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0,
> 0x760005ffbfull, RSP_0),
> @@ -3750,6 +3771,7 @@ __init int intel_pmu_init(void)
>  		x86_pmu.pebs_prec_dist = true;
>  		x86_pmu.lbr_pt_coexist = true;
>  		x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> +		x86_pmu.cpu_events = glm_events_attrs;
>  		pr_cont("Goldmont events, ");
>  		break;
> 
> --
> 2.4.3