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Message-ID: <CAGb2v65cxJqkAzQ-s08qf1J_i8OAZFYc6kqrt3WHV_ACEABtSA@mail.gmail.com>
Date: Thu, 9 Mar 2017 18:10:47 +0800
From: Chen-Yu Tsai <wens@...e.org>
To: Icenowy Zheng <icenowy@...c.xyz>
Cc: Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Chen-Yu Tsai <wens@...e.org>,
Kishon Vijay Abraham I <kishon@...com>,
Hans de Goede <hdegoede@...hat.com>,
devicetree <devicetree@...r.kernel.org>,
linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
linux-kernel <linux-kernel@...r.kernel.org>,
linux-sunxi <linux-sunxi@...glegroups.com>
Subject: Re: [linux-sunxi] [PATCH v3 1/5] dt: bindings: add pmu0 regs for USB
PHYs on Allwinner H3/V3s/A64
On Tue, Mar 7, 2017 at 6:34 AM, Icenowy Zheng <icenowy@...c.xyz> wrote:
> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>
> When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
> tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
>
> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>
> Signed-off-by: Icenowy Zheng <icenowy@...c.xyz>
Acked-by: Chen-Yu Tsai <wens@...e.org>
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