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Message-ID: <lsq.1489146383.628291382@decadent.org.uk>
Date: Fri, 10 Mar 2017 11:46:23 +0000
From: Ben Hutchings <ben@...adent.org.uk>
To: linux-kernel@...r.kernel.org, stable@...r.kernel.org
CC: akpm@...ux-foundation.org, "Ilia Mirkin" <imirkin@...m.mit.edu>,
"Ben Skeggs" <bskeggs@...hat.com>
Subject: [PATCH 3.16 269/370] drm/nouveau/nv1a,nv1f/disp: fix memory clock
rate retrieval
3.16.42-rc1 review patch. If anyone has any objections, please let me know.
------------------
From: Ilia Mirkin <imirkin@...m.mit.edu>
commit 24bf7ae359b8cca165bb30742d2b1c03a1eb23af upstream.
Based on the xf86-video-nv code, NFORCE (NV1A) and NFORCE2 (NV1F) have a
different way of retrieving clocks. See the
nv_hw.c:nForceUpdateArbitrationSettings function in the original code
for how these clocks were accessed.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=54587
Signed-off-by: Ilia Mirkin <imirkin@...m.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@...hat.com>
Signed-off-by: Ben Hutchings <ben@...adent.org.uk>
---
drivers/gpu/drm/nouveau/dispnv04/hw.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--- a/drivers/gpu/drm/nouveau/dispnv04/hw.c
+++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c
@@ -225,6 +225,7 @@ nouveau_hw_get_clock(struct drm_device *
uint32_t mpllP;
pci_read_config_dword(pci_get_bus_and_slot(0, 3), 0x6c, &mpllP);
+ mpllP = (mpllP >> 8) & 0xf;
if (!mpllP)
mpllP = 4;
@@ -235,7 +236,7 @@ nouveau_hw_get_clock(struct drm_device *
uint32_t clock;
pci_read_config_dword(pci_get_bus_and_slot(0, 5), 0x4c, &clock);
- return clock;
+ return clock / 1000;
}
ret = nouveau_hw_get_pllvals(dev, plltype, &pllvals);
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