linux-kernel - Re: [PATCH v5 3/4] dt-bindings: phy: Add support for QMP phy

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <3f6596d9-d1e3-324c-10fb-6c3e65ba724b@codeaurora.org>
Date:   Fri, 10 Mar 2017 11:43:00 +0530
From:   Vivek Gautam <vivek.gautam@...eaurora.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     robh+dt@...nel.org, kishon@...com, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, mark.rutland@....com,
        sboyd@...eaurora.org, srinivas.kandagatla@...aro.org,
        Rob Herring <robh@...nel.org>
Subject: Re: [PATCH v5 3/4] dt-bindings: phy: Add support for QMP phy



On 03/09/2017 04:37 PM, Bjorn Andersson wrote:
> On Thu 09 Mar 10:07 CET 2017, Vivek Gautam wrote:
>
> [..]
>> +	phy@...00 {
>> +		compatible = "qcom,msm8996-qmp-pcie-phy";
>> +		reg = <0x034000 0x488>;
> Drop the leading 0 from the address.

Okay, will drop it.

>
>> +		#clock-cells = <1>;
>> +		#address-cells = <1>;
>> +		#size-cells = <1>;
>> +		ranges;
>> +
>> +		clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
>> +			<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
>> +			<&gcc GCC_PCIE_CLKREF_CLK>;
>> +		clock-names = "aux", "cfg_ahb", "ref";
>> +
>> +		vdda-phy-supply = <&pm8994_l28>;
>> +		vdda-pll-supply = <&pm8994_l12>;
>> +
>> +		resets = <&gcc GCC_PCIE_PHY_BCR>,
>> +			<&gcc GCC_PCIE_PHY_COM_BCR>,
>> +			<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
>> +		reset-names = "phy", "common", "cfg";
>> +
>> +		pciephy_0: lane@0 {
> The "@xyz" part should match the first value in "reg", i.e. 35000 here.

Right, i think this came from my older version of patches. Will correct it.

Regards
Vivek
>
>> +			reg = <0x035000 0x130>,
>> +				<0x035200 0x200>,
>> +				<0x035400 0x1dc>;
>> +			#phy-cells = <0>;
>> +
>> +			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
>> +			clock-names = "pipe0";
>> +			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
>> +			reset-names = "lane0";
>> +		};
>> +
>> +		pciephy_1: lane@1 {
>> +		...
>> +		...
>> +	};
> Regards,
> Bjorn

-- 
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project