linux-kernel - Re: [PATCH] clk: tegra: mark TEGRA210_CLK

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Date:   Mon, 13 Mar 2017 16:18:50 +0200
From:   Peter De Schrijver <pdeschrijver@...dia.com>
To:     Jon Hunter <jonathanh@...dia.com>
CC:     Geert Uytterhoeven <geert@...ux-m68k.org>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Michael Turquette <mturquette@...libre.com>,
        "Stephen Boyd" <sboyd@...eaurora.org>,
        Stephen Warren <swarren@...dotorg.org>,
        "Thierry Reding" <thierry.reding@...il.com>,
        Alexandre Courbot <gnurou@...il.com>,
        linux-clk <linux-clk@...r.kernel.org>,
        <linux-tegra@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] clk: tegra: mark TEGRA210_CLK_DBGAPB as always on

On Mon, Mar 13, 2017 at 11:03:27AM +0000, Jon Hunter wrote:
> 
> On 13/03/17 10:45, Peter De Schrijver wrote:
> > On Wed, Mar 08, 2017 at 11:48:21AM +0000, Jon Hunter wrote:
> >>
> >> On 08/03/17 11:38, Geert Uytterhoeven wrote:
> >>> Hi Jon,
> >>>
> >>> On Wed, Mar 8, 2017 at 11:13 AM, Jon Hunter <jonathanh@...dia.com> wrote:
> >>>>> I had a similar issue with SH-Mobile AG5, where the power domain containing
> >>>>> the JTAG interface is powered down.
> >>>>
> >>>> This reminds me, does your patch assume that the DFD power domain is
> >>>> enabled? I am guessing that it needs to be for JTAG to work.
> >>>
> >>> Yes. The pm-rmobile driver looks for "arm,coresight-etm3x" devices, and
> >>> marks the corresponding PM Domain as always-on, as long as the
> >>> Coresight code doesn't handle runtime PM.
> >>
> >> Sorry Geert, but I was asking Peter specifically about the power-domain
> >> on Tegra as I have a feeling we may have the same scenario ;-)
> > 
> > We don't have a specific power domain for DFD on Tegra210. It's part of the
> > non-powergateable core domain.
> 
> Either we are getting our wires crossed or the TRM is wrong :-(
> 
>  static const char * const tegra210_powergates[] = {
>          [TEGRA_POWERGATE_CPU] = "crail",
>          [TEGRA_POWERGATE_3D] = "3d",
>          [TEGRA_POWERGATE_VENC] = "venc",
>          [TEGRA_POWERGATE_PCIE] = "pcie",
>          [TEGRA_POWERGATE_MPE] = "mpe",
>          [TEGRA_POWERGATE_SATA] = "sata",
>          [TEGRA_POWERGATE_CPU1] = "cpu1",
>          [TEGRA_POWERGATE_CPU2] = "cpu2",
>          [TEGRA_POWERGATE_CPU3] = "cpu3",
>          [TEGRA_POWERGATE_CPU0] = "cpu0",
>          [TEGRA_POWERGATE_C0NC] = "c0nc",
>          [TEGRA_POWERGATE_SOR] = "sor",
>          [TEGRA_POWERGATE_DIS] = "dis",
>          [TEGRA_POWERGATE_DISB] = "disb",
>          [TEGRA_POWERGATE_XUSBA] = "xusba",
>          [TEGRA_POWERGATE_XUSBB] = "xusbb",
>          [TEGRA_POWERGATE_XUSBC] = "xusbc",
>          [TEGRA_POWERGATE_VIC] = "vic",
>          [TEGRA_POWERGATE_IRAM] = "iram",
>          [TEGRA_POWERGATE_NVDEC] = "nvdec",
>          [TEGRA_POWERGATE_NVJPG] = "nvjpg",
>          [TEGRA_POWERGATE_AUD] = "aud",
>          [TEGRA_POWERGATE_DFD] = "dfd",
>          [TEGRA_POWERGATE_VE2] = "ve2",
>  };
> 

This seems to exist indeed. However downstream has never used it, so I wonder
how well powergating this domain has been tested.

Peter.