linux-kernel - [PATCH v2 3/4] x86/mce/AMD: Mark Deferred errors as Action Optional on SMCA systems

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Message-ID: <1490041614-90057-4-git-send-email-Yazen.Ghannam@amd.com>
Date:   Mon, 20 Mar 2017 15:26:53 -0500
From:   Yazen Ghannam <Yazen.Ghannam@....com>
To:     <linux-edac@...r.kernel.org>
CC:     Yazen Ghannam <Yazen.Ghannam@....com>,
        Tony Luck <tony.luck@...el.com>, Borislav Petkov <bp@...e.de>,
        <x86@...nel.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH v2 3/4] x86/mce/AMD: Mark Deferred errors as Action Optional on SMCA systems

From: Yazen Ghannam <yazen.ghannam@....com>

Give Deferred errors an Action Optional severity on SMCA systems so that
the SRAO notifier block can potentially handle them.

Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>
---
Link: http://lkml.kernel.org/r/1486760120-60944-3-git-send-email-Yazen.Ghannam@amd.com

v1->v2:
- New in v2. Based on v1 patch 3.
- Use mce_severity() in AMD interrupt handlers.
- Set proper severity so we can use notifier chain instead of calling
memory_failure() directly.

 arch/x86/kernel/cpu/mcheck/mce-severity.c | 6 +++++-
 arch/x86/kernel/cpu/mcheck/mce_amd.c      | 4 ++++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce-severity.c b/arch/x86/kernel/cpu/mcheck/mce-severity.c
index 87cc9ab..2773c85 100644
--- a/arch/x86/kernel/cpu/mcheck/mce-severity.c
+++ b/arch/x86/kernel/cpu/mcheck/mce-severity.c
@@ -278,8 +278,12 @@ static int mce_severity_amd(struct mce *m, int tolerant, char **msg, bool is_exc
 	 * deferred error: poll handler catches these and adds to mce_ring so
 	 * memory-failure can take recovery actions.
 	 */
-	if (m->status & MCI_STATUS_DEFERRED)
+	if (m->status & MCI_STATUS_DEFERRED) {
+		if (mce_flags.smca)
+			return MCE_AO_SEVERITY;
+
 		return MCE_DEFERRED_SEVERITY;
+	}
 
 	/*
 	 * corrected error: poll handler catches these and passes responsibility
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 10fddcc..743ae31 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -28,6 +28,8 @@
 #include <asm/msr.h>
 #include <asm/trace/irq_vectors.h>
 
+#include "mce-internal.h"
+
 #define NR_BLOCKS         5
 #define THRESHOLD_MAX     0xFFF
 #define INT_TYPE_APIC     0x00020000
@@ -802,6 +804,8 @@ __log_error(unsigned int bank, bool deferred_err, bool threshold_err, u64 misc)
 	m.bank   = bank;
 	m.tsc	 = rdtsc();
 
+	m.severity = mce_severity(&m, mca_cfg.tolerant, NULL, false);
+
 	if (threshold_err)
 		m.misc = misc;
 
-- 
2.7.4