linux-kernel - Re: [PATCH v15 6/9] x86/arch_prctl: Add ARCH_[GET|SET]

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Message-ID: <CAP045AoSC_KXrGyscnZiqnvtdr_e6PmmZ4RiD4CEgc_5RiHbhw@mail.gmail.com>
Date:   Mon, 20 Mar 2017 01:01:54 -0700
From:   Kyle Huey <me@...ehuey.com>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     "Robert O'Callahan" <robert@...llahan.org>,
        Andy Lutomirski <luto@...nel.org>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>,
        "maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)" <x86@...nel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Jeff Dike <jdike@...toit.com>,
        Richard Weinberger <richard@....at>,
        Alexander Viro <viro@...iv.linux.org.uk>,
        Shuah Khan <shuah@...nel.org>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Borislav Petkov <bp@...e.de>,
        Peter Zijlstra <peterz@...radead.org>,
        Boris Ostrovsky <boris.ostrovsky@...cle.com>,
        Len Brown <len.brown@...el.com>,
        Dmitry Safonov <dsafonov@...tuozzo.com>,
        "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>,
        David Matlack <dmatlack@...gle.com>,
        Nadav Amit <nadav.amit@...il.com>,
        Andi Kleen <andi@...stfloor.org>,
        open list <linux-kernel@...r.kernel.org>,
        "open list:USER-MODE LINUX (UML)" 
        <user-mode-linux-devel@...ts.sourceforge.net>,
        "open list:USER-MODE LINUX (UML)" 
        <user-mode-linux-user@...ts.sourceforge.net>,
        "open list:KERNEL SELFTEST FRAMEWORK" 
        <linux-kselftest@...r.kernel.org>, kvm list <kvm@...r.kernel.org>
Subject: Re: [PATCH v15 6/9] x86/arch_prctl: Add ARCH_[GET|SET]_CPUID

On Tue, Mar 14, 2017 at 1:36 PM, Thomas Gleixner <tglx@...utronix.de> wrote:
> On Sat, 11 Mar 2017, Kyle Huey wrote:
>>  static void init_intel_misc_features(struct cpuinfo_x86 *c)
>>  {
>>       u64 msr;
>>
>> +     if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
>> +             return;
>> +
>> +     msr = 0;
>> +     wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
>> +     this_cpu_write(msr_misc_features_shadow, msr);
>> +
>>       if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
>>               if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
>>                       set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
>>       }
>>
>>       probe_xeon_phi_r3mwait(c);
>
> The way you are doing it breaks the ring3 mwait feature because you
> overwrite the R3MWAIT bit the first time you update the MSR on context
> switch.

Indeed.  Good catch.

- Kyle