linux-kernel - [tip:x86/process] x86/cpufeature: Detect CPUID faulting support

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Message-ID: <tip-90218ac77d0582eaf2d0872d8d900cbd5bf1f205@git.kernel.org>
Date:   Mon, 20 Mar 2017 09:34:22 -0700
From:   tip-bot for Kyle Huey <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     boris.ostrovsky@...cle.com, pbonzini@...hat.com,
        robert@...llahan.org, khuey@...ehuey.com, me@...ehuey.com,
        viro@...iv.linux.org.uk, andi@...stfloor.org,
        rafael.j.wysocki@...el.com, richard@....at,
        grzegorz.andrejczuk@...el.com, hpa@...or.com, bp@...e.de,
        rkrcmar@...hat.com, tglx@...utronix.de, dsafonov@...tuozzo.com,
        dave.hansen@...ux.intel.com, mingo@...nel.org, dmatlack@...gle.com,
        peterz@...radead.org, shuah@...nel.org,
        linux-kernel@...r.kernel.org, jdike@...toit.com, luto@...nel.org,
        len.brown@...el.com, nadav.amit@...il.com
Subject: [tip:x86/process] x86/cpufeature: Detect CPUID faulting support

Commit-ID:  90218ac77d0582eaf2d0872d8d900cbd5bf1f205
Gitweb:     http://git.kernel.org/tip/90218ac77d0582eaf2d0872d8d900cbd5bf1f205
Author:     Kyle Huey <me@...ehuey.com>
AuthorDate: Mon, 20 Mar 2017 01:16:25 -0700
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Mon, 20 Mar 2017 16:10:34 +0100

x86/cpufeature: Detect CPUID faulting support

Intel supports faulting on the CPUID instruction beginning with Ivy Bridge.
When enabled, the processor will fault on attempts to execute the CPUID
instruction with CPL>0. This will allow a ptracer to emulate the CPUID
instruction.

Bit 31 of MSR_PLATFORM_INFO advertises support for this feature. It is
documented in detail in Section 2.3.2 of
https://bugzilla.kernel.org/attachment.cgi?id=243991

Detect support for this feature and expose it as X86_FEATURE_CPUID_FAULT.

Signed-off-by: Kyle Huey <khuey@...ehuey.com>
Reviewed-by: Borislav Petkov <bp@...e.de>
Cc: Grzegorz Andrejczuk <grzegorz.andrejczuk@...el.com>
Cc: kvm@...r.kernel.org
Cc: Radim Krčmář <rkrcmar@...hat.com>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Andi Kleen <andi@...stfloor.org>
Cc: linux-kselftest@...r.kernel.org
Cc: Nadav Amit <nadav.amit@...il.com>
Cc: Robert O'Callahan <robert@...llahan.org>
Cc: Richard Weinberger <richard@....at>
Cc: "Rafael J. Wysocki" <rafael.j.wysocki@...el.com>
Cc: Andy Lutomirski <luto@...nel.org>
Cc: Len Brown <len.brown@...el.com>
Cc: Shuah Khan <shuah@...nel.org>
Cc: user-mode-linux-devel@...ts.sourceforge.net
Cc: Jeff Dike <jdike@...toit.com>
Cc: Alexander Viro <viro@...iv.linux.org.uk>
Cc: user-mode-linux-user@...ts.sourceforge.net
Cc: David Matlack <dmatlack@...gle.com>
Cc: Boris Ostrovsky <boris.ostrovsky@...cle.com>
Cc: Dmitry Safonov <dsafonov@...tuozzo.com>
Cc: linux-fsdevel@...r.kernel.org
Cc: Paolo Bonzini <pbonzini@...hat.com>
Link: http://lkml.kernel.org/r/20170320081628.18952-8-khuey@kylehuey.com
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>

---
 arch/x86/include/asm/cpufeatures.h |  1 +
 arch/x86/include/asm/msr-index.h   |  2 ++
 arch/x86/kernel/cpu/intel.c        | 24 +++++++++++++++++++++++-
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index b04bb6d..0fe0044 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -187,6 +187,7 @@
  * Reuse free bits when adding new feature flags!
  */
 #define X86_FEATURE_RING3MWAIT	( 7*32+ 0) /* Ring 3 MONITOR/MWAIT */
+#define X86_FEATURE_CPUID_FAULT ( 7*32+ 1) /* Intel CPUID faulting */
 #define X86_FEATURE_CPB		( 7*32+ 2) /* AMD Core Performance Boost */
 #define X86_FEATURE_EPB		( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
 #define X86_FEATURE_CAT_L3	( 7*32+ 4) /* Cache Allocation Technology L3 */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index f429b70..b1f75da 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -45,6 +45,8 @@
 #define MSR_IA32_PERFCTR1		0x000000c2
 #define MSR_FSB_FREQ			0x000000cd
 #define MSR_PLATFORM_INFO		0x000000ce
+#define MSR_PLATFORM_INFO_CPUID_FAULT_BIT	31
+#define MSR_PLATFORM_INFO_CPUID_FAULT		BIT_ULL(MSR_PLATFORM_INFO_CPUID_FAULT_BIT)
 
 #define MSR_PKG_CST_CONFIG_CONTROL	0x000000e2
 #define NHM_C3_AUTO_DEMOTE		(1UL << 25)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index e229318..a07f829 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -488,6 +488,28 @@ static void intel_bsp_resume(struct cpuinfo_x86 *c)
 	init_intel_energy_perf(c);
 }
 
+static void init_cpuid_fault(struct cpuinfo_x86 *c)
+{
+	u64 msr;
+
+	if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
+		if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
+			set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
+	}
+}
+
+static void init_intel_misc_features(struct cpuinfo_x86 *c)
+{
+	u64 msr;
+
+	if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
+		return;
+
+	/* Check features and update capabilities */
+	init_cpuid_fault(c);
+	probe_xeon_phi_r3mwait(c);
+}
+
 static void init_intel(struct cpuinfo_x86 *c)
 {
 	unsigned int l2 = 0;
@@ -602,7 +624,7 @@ static void init_intel(struct cpuinfo_x86 *c)
 
 	init_intel_energy_perf(c);
 
-	probe_xeon_phi_r3mwait(c);
+	init_intel_misc_features(c);
 }
 
 #ifdef CONFIG_X86_32