linux-kernel - Re: [PATCH v12 4/9] mmc: cavium: Work-around hardware bug on cn6xxx and cnf7xxx

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Date:   Tue, 21 Mar 2017 08:19:38 -0700
From:   David Daney <ddaney@...iumnetworks.com>
To:     Arnd Bergmann <arnd@...db.de>
Cc:     Ulf Hansson <ulf.hansson@...aro.org>,
        Jan Glauber <jglauber@...ium.com>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Steven J . Hill" <Steven.Hill@...ium.com>,
        David Daney <david.daney@...ium.com>
Subject: Re: [PATCH v12 4/9] mmc: cavium: Work-around hardware bug on cn6xxx
 and cnf7xxx

On 03/21/2017 01:58 AM, Arnd Bergmann wrote:
> On Mon, Mar 20, 2017 at 9:45 PM, David Daney <ddaney@...iumnetworks.com> wrote:
>> On 03/17/2017 07:13 AM, Ulf Hansson wrote:
>>> My point is really that we should avoid exporting SoC specific APIs
>>> which shall be called from drivers. This is old fashion.
>>
>>
>> Some people find it objectionable to see 1-off architecture specific in-line
>> asm in a driver file, but I agree that putting it as close to the user as
>> possible makes sense.
>
> The proper solution might be to create an architecture independent interface
> for it, what it is that the function does. Can you explain what the purpose
> of locking/unlocking the cache line for MMC is? Is this something that
> could be done more generally in the dma_map_ops implementation?

It is a 1-off erratum workaround that is only needed on fewer than five 
models/revisions of a mips64 based SoC family.  As such, creating a 
general purpose, architecture independent, framework is clearly not the 
proper approach.  This is a problem that effects only the Cavium MMC bus 
hardware block as implemented on a mips64 based SoC.  The arm64 based 
SoCs do not have this problem, and and future users of the block will 
also not contain the erratum. That is what it is.

At a high level, its purpose is to eliminate data corruption when doing 
DMA write operations to transfer data into the SD/MMC devices.  The 
specific details and RTL code for effected SoCs will not be made public. 
  It should be enough to know that the 2nd-to-last cache block of a 
transfer must be locked in the L2 cache to ensure reliable operation on 
DMA writes.  This is not some empirically derived workaround, but rather 
it is based on a well understood root cause of the failure case.

David.