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Message-ID: <20170323203138.li45llrzfxcaqieu@hirez.programming.kicks-ass.net>
Date: Thu, 23 Mar 2017 21:31:38 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: kan.liang@...el.com
Cc: mingo@...hat.com, acme@...nel.org, linux-kernel@...r.kernel.org,
tglx@...utronix.de, eranian@...gle.com, jolsa@...nel.org,
ak@...ux.intel.com
Subject: Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI
On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.liang@...el.com wrote:
> From: Kan Liang <Kan.liang@...el.com>
>
> When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance
> counters will be effected. There is no way to do per-counter freeze
> on smi. So it should not use the per-event interface (e.g. ioctl or
> event attribute) to set FREEZE_WHILE_SMM bit.
>
> Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM
> bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages
> while in SMM.
> Value has to be 0 or 1. It will be applied to all possible cpus.
So is there ever a good reason to not set this?
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