linux-kernel - RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

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Message-ID: <37D7C6CF3E00A74B8858931C1DB2F077536BE9A6@SHSMSX103.ccr.corp.intel.com>
Date:   Thu, 23 Mar 2017 20:48:06 +0000
From:   "Liang, Kan" <kan.liang@...el.com>
To:     Peter Zijlstra <peterz@...radead.org>
CC:     "mingo@...hat.com" <mingo@...hat.com>,
        "acme@...nel.org" <acme@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "eranian@...gle.com" <eranian@...gle.com>,
        "jolsa@...nel.org" <jolsa@...nel.org>,
        "ak@...ux.intel.com" <ak@...ux.intel.com>
Subject: RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

> On Thu, Mar 23, 2017 at 11:25:49AM -0700, kan.liang@...el.com wrote:
> > From: Kan Liang <Kan.liang@...el.com>
> >
> > When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all
> performance
> > counters will be effected. There is no way to do per-counter freeze on
> > smi. So it should not use the per-event interface (e.g. ioctl or event
> > attribute) to set FREEZE_WHILE_SMM bit.
> >
> > Adds sysfs entry /sys/device/cpu/freeze_on_smi to set
> FREEZE_WHILE_SMM
> > bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages
> > while in SMM.
> > Value has to be 0 or 1. It will be applied to all possible cpus.
> 
> So is there ever a good reason to not set this?

For me, I don't see any drawbacks to set it unconditionally.
But I'm not sure if there is someone else who may want the counter
running in SMI.

If there is no objection, I will set the FREEZE_WHILE_SMM bit
unconditionally in next version.

Thanks,
Kan