linux-kernel - Re: [PATCH 0/9] bus: brcmstb_gisb: add support for GISBv7 arbiter

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20170324150355.GC29588@leverpostej>
Date:   Fri, 24 Mar 2017 15:03:55 +0000
From:   Mark Rutland <mark.rutland@....com>
To:     Doug Berger <opendmb@...il.com>
Cc:     catalin.marinas@....com, robh+dt@...nel.org, will.deacon@....com,
        computersforpeace@...il.com, gregory.0xf0@...il.com,
        f.fainelli@...il.com, bcm-kernel-feedback-list@...adcom.com,
        wangkefeng.wang@...wei.com, james.morse@....com,
        vladimir.murzin@....com, panand@...hat.com, andre.przywara@....com,
        cmetcalf@...lanox.com, mingo@...nel.org,
        sandeepa.s.prabhu@...il.com, shijie.huang@....com,
        linus.walleij@...aro.org, treding@...dia.com, jonathanh@...dia.com,
        olof@...om.net, mirza.krak@...il.com, suzuki.poulose@....com,
        bgolaszewski@...libre.com, horms+renesas@...ge.net.au,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH 0/9] bus: brcmstb_gisb: add support for GISBv7 arbiter

On Fri, Mar 24, 2017 at 07:46:23AM -0700, Doug Berger wrote:
> This patch set contains changes to enable the GISB arbiter driver
> on the latest ARM64 architecture Set-Top Box chips from Broadcom.
> 
> This driver relies on being able to hook the abort handlers of
> the processor core that are triggered by bus error signals
> generated by the GISB bus arbiter hardware found in BCM7XXX chips.

Ugh; hardware generating asynchonous exceptions is hideous. I had hoped
that such hardware was a thing of the past.

Under what circumstances does the GISB bus arbiter generate these
aborts?

Mark.

> The first three patches are based on the arm64/for-next/core
> branch to enable this functionality for the arm64 architecture.
> 
> The remaining patches correct some issues with the existing driver,
> add the ARM64 architecture specific support to the driver, and
> finally add the new register map for the GISBv7 hardware first
> appearing in the BCM7278 device.
> 
> Doug Berger (7):
>   arm64: mm: mark fault_info __ro_after_init
>   arm64: mm: install SError abort handler
>   bus: brcmstb_gisb: Use register offsets with writes too
>   bus: brcmstb_gisb: Correct hooking of ARM aborts
>   bus: brcmstb_gisb: correct support for 64-bit address output
>   bus: brcmstb_gisb: add ARM64 SError support
>   bus: brcmstb_gisb: update to support new revision
> 
> Florian Fainelli (2):
>   arm64: mm: Allow installation of memory abort handlers
>   bus: brcmstb_gisb: Add ARM64 support
> 
>  .../devicetree/bindings/bus/brcm,gisb-arb.txt      |   3 +-
>  arch/arm64/include/asm/system_misc.h               |   5 +
>  arch/arm64/kernel/entry.S                          |  69 ++++++++++++--
>  arch/arm64/mm/fault.c                              |  48 +++++++++-
>  drivers/bus/Kconfig                                |   2 +-
>  drivers/bus/brcmstb_gisb.c                         | 106 ++++++++++++++++-----
>  6 files changed, 197 insertions(+), 36 deletions(-)
> 
> -- 
> 2.12.0
>